Rajiv V. Joshi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
49
Venues
11
Active years
1997–2026
Best venue rank
A*
Where they publish
Papers
49 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISCAS | Mixed-Mode ReRAM Architecture with Digital Weights and Inputs for High-Precision In-Memory Computing. | Nithin Krishnan, Rajiv V. Joshi, Alex James |
| 2025 | ICCAD | Energy-Efficient Multi-Operand XOR Logic-Based CIM Accelerator using RRAM technology. | Abhairaj Singh, Konstantinos Stavrakakis, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui |
| 2025 | ISLPED | Design Techniques for Ultra-low Power Cryogenic CMOS for Quantum Computing Applications. | Sudipto Chakraborty, Pat Rosno, John F. Bulzacchelli, David J. Frank, Rajiv V. Joshi, Daniel J. Friedman |
| 2024 | ISCAS | SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin. | Dinesh Kushwaha, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu |
| 2023 | DAC | (Invited) Predictive analytics for cryogenic CMOS in future quantum computing systems. | Rajiv V. Joshi, Sudipto Chakraborty |
| 2023 | VLSID | An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. | Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu |
| 2022 | DATE | Referencing-in-Array Scheme for RRAM-based CIM Architecture. | Abhairaj Singh, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui |
| 2022 | DATE | A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation. | Kevin Tien, Ken Inoue, Scott Lekuch, David J. Frank, Sudipto Chakraborty, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman |
| 2022 | ISCAS | A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. | Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu |
| 2022 | ITC | Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT. | Abhairaj Singh, Moritz Fieback, Rajendra Bishnoi, Filip Bradaric, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui |
| 2021 | ISCAS | Low-Power Memristor-Based Computing for Edge-AI Applications. | Abhairaj Singh, Sumit Diware, Anteneh Gebregiorgis, Rajendra Bishnoi, Francky Catthoor, Rajiv V. Joshi, Said Hamdioui |
| 2020 | DAC | Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation. | Gouranga Charan, Jubin Hazra, Karsten Beckmann, Xiaocong Du, Gokul Krishnan, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao |
| 2019 | HPCA | Resilient Low Voltage Accelerators for High Energy Efficiency. | Nandhini Chandramoorthy, Karthik Swaminathan, Martin Cochet, Arun Paidimarri, Schuyler Eldridge, Rajiv V. Joshi, Matthew M. Ziegler, Alper Buyuktosunoglu, Pradip Bose |
| 2019 | ISCAS | Data Imbalance Handling Approaches for Accurate Statistical Modeling and Yield Analysis of Memory Designs. | Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi |
| 2017 | ICCD | Very Low Voltage (VLV) Design. | Ramon Bertran, Pradip Bose, David M. Brooks, Jeff Burns, Alper Buyuktosunoglu, Nandhini Chandramoorthy, Eric Cheng, Martin Cochet, Schuyler Eldridge, Daniel J. Friedman, Hans M. Jacobson, Rajiv V. Joshi, Subhasish Mitra, Robert K. Montoye, Arun Paidimarri, Pritish Parida, Kevin Skadron, Mircea Stan, Karthik Swaminathan, Augusto Vega, Swagath Venkataramani, Christos Vezyrtzis, Gu-Yeon Wei, John-David Wellman, Matthew M. Ziegler |
| 2016 | ISCAS | Big biomedical image processing hardware acceleration: A case study for K-means and image filtering. | Katayoun Neshatpour, Arezou Koohi, Farnoud Farahmand, Rajiv V. Joshi, Setareh Rafatirad, Avesta Sasan, Houman Homayoun |
| 2016 | ISPASS | Characterizing Hadoop applications on microservers for performance and energy efficiency optimizations. | Maria Malik, Avesta Sasan, Rajiv V. Joshi, Setareh Rafatirah, Houman Homayoun |
| 2014 | DAC | A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability. | Enes Eken, Yaojun Zhang, Wujie Wen, Rajiv V. Joshi, Hai Li, Yiran Chen |
| 2013 | VLSID | Hardware-corroborated Variability-Aware SRAM Methodology. | Rajiv V. Joshi, Rouwaida Kanj, S. Butt, Emrah Acar, Dallas Lea, D. Sciacca |
| 2012 | DAC | Yield estimation via multi-cones. | Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jerry Hayes, Sani R. Nassif |
| 2012 | ICCAD | A thermal and process variation aware MTJ switching model and its applications in soft error analysis. | Peiyuan Wang, Wei Zhang, Rajiv V. Joshi, Rouwaida Kanj, Yiran Chen |
| 2011 | ICCAD | Universal statistical cure for predicting memory loss. | Rajiv V. Joshi, Rouwaida Kanj, Peiyuan Wang, Hai Li |
| 2011 | ICCAD | Accelerated statistical simulation via on-demand Hermite spline interpolations. | Rouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif |
| 2010 | ISLPED | Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives. | Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif |
| 2010 | VLSID | FinFET SRAM Design. | Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj |
| 2009 | ICCAD | An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. | Rouwaida Kanj, Rajiv V. Joshi, Chad Adams, James D. Warnock, Sani R. Nassif |
| 2008 | ISLPED | SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. | Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jente B. Kuang, Hung C. Ngo, Nancy Ying Zhou, Weiping Shi, Sani R. Nassif |
| 2007 | ISLPED | A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. | Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang |
| 2007 | VLSID | A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. | Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang |
| 2006 | DAC | A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. | Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee |
| 2006 | DAC | Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. | Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif |
| 2006 | VLSID | Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. | Ruchir Puri, Tanay Karnik, Rajiv V. Joshi |
| 2005 | ICCD | A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction. | Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, Jethro C. Law, Rajiv V. Joshi |
| 2005 | VLSID | Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. | Rajiv V. Joshi, S. S. Kang, N. Zamdmar, Anda Mocuta, Ching-Te Chuang, J. A. Pascual-Gutirrez |
| 2004 | ISLPED | Nanoscale CMOS circuit leakage power reduction by double-gate device. | Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang |
| 2004 | VLSID | A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI. | Rajiv V. Joshi, K. Kroell, Ching-Te Chuang |
| 2003 | ICCAD | Design and CAD Challenges in sub-90nm CMOS Technologies. | Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri |
| 2003 | ISLPED | New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. | Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown |
| 2003 | ISLPED | Strained-si devices and circuits for low-power applications. | Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang |
| 2003 | VLSID | Design of Deep Sub-Micron CMOS Circuits. | Rajiv V. Joshi, Kaushik Roy |
| 2001 | ISLPED | Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. | W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi |
| 2001 | VLSID | Design Of Provably Correct Storage Arrays. | Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann |
| 2001 | VLSID | IBM's Blue Logic Design Methodology-Circuits and Physical Design. | Ruchira Kamdar, Seetharam Gundurao, Rajiv V. Joshi, N. S. Murty |
| 2000 | ISLPED | "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). | Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang |
| 2000 | VLSID | A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25m SOI Technology. | Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang |
| 1999 | VLSID | Design Considerations and Implementation of a High Performance Dynamic Register File. | Rajiv V. Joshi, Wei Hwang |
| 1998 | VTS | Designing a Testable System on a Chip. | Stephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Benjamin D. Parker, T. V. Rajeevakumar, Kevin Stawiasz |
| 1997 | ICCD | A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. | Wei Hwang, Rajiv V. Joshi, Walter H. Henkels |
| 1997 | ICCD | Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. | W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, Hing Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi |