| 2017 | ISCAS | Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations. | Chia-Ning Chang, Yin-Nien Chen, Po-Tsang Huang, Pin Su, Ching-Te Chuang |
| 2017 | ISCAS | An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. | Po-Tsang Huang, Yu-Chieh Huang, Shang-Lin Wu, Yu-Chen Hu, Ming-Wei Lu, Ting-Wei Sheng, Fung-Kai Chang, Chun-Pin Lin, Nien-Shang Chang, Hung-Lieh Chen, Chi-Shi Chen, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou |
| 2016 | ISCAS | A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. | Yi-Wei Chiu, Yu-Hao Hu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang |
| 2016 | ISCAS | An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes. | Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou |
| 2016 | ISCAS | Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs. | Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang |
| 2016 | ISLPED | Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells. | Chang-Hung Yu, Pin Su, Ching-Te Chuang |
| 2015 | ISCAS | Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness. | Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang |
| 2015 | ISCAS | Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells. | Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang |
| 2014 | ISCAS | Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling. | Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang |
| 2014 | ISCAS | Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells. | Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang |
| 2014 | ISCAS | Energy-efficient configurable discrete wavelet transform for neural sensing applications. | Tang-Hsuan Wang, Po-Tsang Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang |
| 2014 | ISLPED | Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell. | Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang |
| 2013 | ISCAS | Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection. | Ming-Hung Chang, Shang-Yuan Lin, Pei-Chen Wu, Olesya Zakoretska, Ching-Te Chuang, Kuan-Neng Chen, Chen-Chao Wang, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang |
| 2013 | ISCAS | A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. | Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih |
| 2013 | ISLPED | A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. | Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang |
| 2012 | ISCAS | An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. | Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu |
| 2012 | ISCAS | High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. | Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu |
| 2012 | ISLPED | A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. | Yi-Wei Lin, Hao-I Yang, Geng-Cing Lin, Chi-Shin Chang, Ching-Te Chuang, Wei Hwang, Chia-Cheng Chen, Willis Shih, Huan-Shun Huang |
| 2012 | ITC | Testing strategies for a 9T sub-threshold SRAM. | Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, Mango Chia-Tso Chao, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang |
| 2011 | ISLPED | 8T single-ended sub-threshold SRAM with cross-point data-aware write operation. | Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang |
| 2011 | ISLPED | Analysis of power-performance for ultra-thin-body GeOI logic circuits. | Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang |
| 2009 | ICCAD | Yield estimation of SRAM circuits using "Virtual SRAM Fab". | Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das |
| 2009 | ISCAS | Modeling, Analysis, and TCAD of Nanoscale Devices and Circuits. | Ching-Te Chuang |
| 2009 | ISCAS | A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry. | Amlan Ghosh, Richard B. Brown, Rahul M. Rao, Ching-Te Chuang |
| 2009 | ISCAS | Impacts of NBTI and PBTI on Power-gated SRAM with High-k Metal-gate Devices. | Hao-I Yang, Ching-Te Chuang, Wei Hwang |
| 2009 | ISLPED | Design and analysis of ultra-thin-body SOI based subthreshold SRAM. | Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang |
| 2008 | ICCD | Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. | Aditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang |
| 2008 | ISCAS | Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. | Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang |
| 2008 | VLSID | Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. | Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy |
| 2008 | VLSID | On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. | Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown |
| 2008 | VTS | Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. | Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy |
| 2007 | ISLPED | A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. | Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang |
| 2007 | ISLPED | Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies. | Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang |
| 2007 | VLSID | A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. | Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang |
| 2006 | VLSID | High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header. | Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang |
| 2005 | ISLPED | Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. | Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy |
| 2005 | VLSID | Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. | Rajiv V. Joshi, S. S. Kang, N. Zamdmar, Anda Mocuta, Ching-Te Chuang, J. A. Pascual-Gutirrez |
| 2004 | ISLPED | Nanoscale CMOS circuit leakage power reduction by double-gate device. | Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang |
| 2004 | VLSID | A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI. | Rajiv V. Joshi, K. Kroell, Ching-Te Chuang |
| 2003 | ICCAD | Design and CAD Challenges in sub-90nm CMOS Technologies. | Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri |
| 2003 | ISLPED | New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. | Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown |
| 2003 | ISLPED | Strained-si devices and circuits for low-power applications. | Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang |
| 2000 | ISLPED | "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). | Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang |
| 2000 | VLSID | A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25m SOI Technology. | Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang |
| 2000 | VLSID | SOI Digital Circuits: Design Issues. | Ruchir Puri, Ching-Te Chuang |
| 1999 | DAC | SOI Digital CMOS VLSI - a Design Perspective. | Ching-Te Chuang, Ruchir Puri |
| 1999 | ISLPED | Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits. | Ruchir Puri, Ching-Te Chuang |
| 1996 | ISLPED | Floating body effects in partially-depleted SOI CMOS circuits. | Pong-Fei Lu, Jin Ji, Ching-Te Chuang, Lawrence F. Wagner, Chang-Ming Hsieh, Jente Benedict Kuang, L. Hsu, Mario M. Pelella Jr., Shao-Fu Sanford Chu, Carl J. Anderson |