| 2017 | ISCAS | An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. | Po-Tsang Huang, Yu-Chieh Huang, Shang-Lin Wu, Yu-Chen Hu, Ming-Wei Lu, Ting-Wei Sheng, Fung-Kai Chang, Chun-Pin Lin, Nien-Shang Chang, Hung-Lieh Chen, Chi-Shi Chen, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou |
| 2016 | ISCAS | An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes. | Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou |
| 2015 | ISCAS | An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications. | Chung-Shiang Wu, Kai-Chun Lin, Yi-Ping Kuo, Po-Hung Chen, Yuan-Hua Chu, Wei Hwang |
| 2014 | ISCAS | Energy-efficient configurable discrete wavelet transform for neural sensing applications. | Tang-Hsuan Wang, Po-Tsang Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang |
| 2013 | ISCAS | Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection. | Ming-Hung Chang, Shang-Yuan Lin, Pei-Chen Wu, Olesya Zakoretska, Ching-Te Chuang, Kuan-Neng Chen, Chen-Chao Wang, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang |
| 2013 | ISCAS | A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. | Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih |
| 2012 | ISCAS | Substrate noise suppression technique for power integrity of TSV 3D integration. | Po-Jen Yang, Po-Tsang Huang, Wei Hwang |
| 2012 | ISCAS | High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. | Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu |
| 2012 | ISLPED | A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. | Yi-Wei Lin, Hao-I Yang, Geng-Cing Lin, Chi-Shin Chang, Ching-Te Chuang, Wei Hwang, Chia-Cheng Chen, Willis Shih, Huan-Shun Huang |
| 2011 | ISLPED | A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS. | Ming-Hung Chang, Yi-Te Chiu, Shu-Lin Lai, Wei Hwang |
| 2011 | ISLPED | Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation. | Ming-Hung Chang, Chung-Ying Hsieh, Mei-Wei Chen, Wei Hwang |
| 2010 | ISCAS | Fully on-chip temperature, process, and voltage sensors. | Shi-Wen Chen, Ming-Hung Chang, Wei-Chih Hsieh, Wei Hwang |
| 2010 | ISCAS | Low quiescent current variable output digital controlled voltage regulator. | Wei-Chih Hsieh, Wei Hwang |
| 2009 | ISCAS | Impacts of NBTI and PBTI on Power-gated SRAM with High-k Metal-gate Devices. | Hao-I Yang, Ching-Te Chuang, Wei Hwang |
| 2008 | ISCAS | A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. | Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang |
| 2008 | ISCAS | "Green" micro-architecture and circuit co-design for ternary content addressable memory. | Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang |
| 2007 | ISCAS | A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation. | Ming-Hung Chang, Zong-Xi Yang, Wei Hwang |
| 2007 | ISCAS | Low Power On-Chip Current Monitoring Medium-Grained Adaptive Voltage Control. | Wei-Chih Hsieh, Wei Hwang |
| 2006 | ISCAS | A 1.7mW all digital phase-locked loop with new gain generator and low power DCO. | Tzu-Chiang Chao, Wei Hwang |
| 2006 | ISCAS | 2-level FIFO architecture design for switch fabrics in network-on-chip. | Po-Tsang Huang, Wei Hwang |
| 2006 | ISCAS | A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM. | Chung-Hsien Hua, Chi-Wei Peng, Wei Hwang |
| 2005 | ISCAS | Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits. | Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen |
| 2001 | ISLPED | Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. | W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi |
| 2001 | VLSID | Design Of Provably Correct Storage Arrays. | Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann |
| 2000 | ISLPED | "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). | Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang |
| 2000 | VLSID | A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25m SOI Technology. | Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang |
| 1999 | VLSID | Design Considerations and Implementation of a High Performance Dynamic Register File. | Rajiv V. Joshi, Wei Hwang |
| 1997 | ICCD | A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. | Wei Hwang, Rajiv V. Joshi, Walter H. Henkels |
| 1997 | ICCD | Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. | W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, Hing Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi |