Integrated Verification Approach during ADL-Driven Processor Design.
Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
VenueCRSP
Year2006
ProceedingsIEEE International Workshop on Rapid System Prototyping
DBLP recordconf/rsp/ChattopadhyaySZLAM06 ↗
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