Rainer Leupers
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
135
Venues
25
Active years
1993–2026
Best venue rank
A*
Where they publish
- ADATE52 papers
- A*DAC16 papers
- BASPDAC13 papers
- CSCOPES10 papers
- NationalVLSID7 papers
- AICCAD5 papers
- CICCD4 papers
- CISCAS3 papers
- CFDL3 papers
- CRSP3 papers
- CDSD2 papers
- Journal PublishedCASES2 papers
- CHPCC2 papers
- BPPoPP2 papers
- BIJCNN1 paper
- BFPL1 paper
- AISSRE1 paper
- BETS1 paper
- CVEHITS1 paper
- BTrustCom1 paper
- CIPCCC1 paper
- CISPA1 paper
- BCC1 paper
- MulticonferenceICASSP1 paper
- A*PLDI1 paper
Papers
135 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DATE | Mixed-Precision Training and Compilation for RRAM-based Computing-in-Memory Accelerators. | Rebecca Pelke, Joel Klein, Jos Cubero-Cascante, Nils Bosbach, Jan Moritz Joseph, Rainer Leupers |
| 2025 | DAC | Introducing Instruction-Accurate Simulators for Performance Estimation of Autotuning Workloads. | Rebecca Pelke, Nils Bosbach, Lennart M. Reimann, Rainer Leupers |
| 2025 | DATE | High-Performance ARM-on-ARM Virtualization for Multicore SystemC-TLM-Based Virtual Platforms. | Nils Bosbach, Rebecca Pelke, Niko Zurstraen, Jan Henrik Weinstock, Lukas Jnger, Rainer Leupers |
| 2025 | DATE | Static Global Register Allocation for Dynamic Binary Translators. | Niko Zurstraen, Nils Bosbach, Lennart M. Reimann, Rainer Leupers |
| 2025 | DATE | FloppyFloat: An Open Source Floating Point Library for Instruction Set Simulators. | Niko Zurstraen, Nils Bosbach, Rainer Leupers |
| 2025 | ICCAD | Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors. | Evgenii Rezunov, Niko Zurstraen, Lennart M. Reimann, Rainer Leupers |
| 2024 | ASPDAC | The Optimal Quantum of Temporal Decoupling. | Niko Zurstraen, Ruben Brandhofer, Jos Cubero-Cascante, Nils Bosbach, Lukas Jnger, Rainer Leupers |
| 2024 | DAC | Towards High-Performance Virtual Platforms: A Parallelization Strategy for SystemC TLM-2.0 CPU Models. | Nils Bosbach, Niko Zurstraen, Rebecca Pelke, Lukas Jnger, Jan Henrik Weinstock, Rainer Leupers |
| 2024 | DATE | CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures. | Rebecca Pelke, Jos Cubero-Cascante, Nils Bosbach, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph |
| 2024 | IJCNN | Spiking Neural Networks for Signal Classification with Digital and Analog Neuromorphic Systems: A Comparative Study. | Leon Happek, Jen-Tse Huang, Alejandro Garcia Gener, Rainer Leupers, Melvin Galicia |
| 2023 | DAC | Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. | Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letcia Maria Bolzani Phls, Rainer Leupers |
| 2023 | DATE | ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. | Gia Bao Thieu, Sven Gesper, Guillermo Pay-Vay, Christoph Riggers, Oliver Renke, Till Fiedler, Jakob Marten, Tobias Stuckenberg, Holger Blume, Christian Weis, Lukas Steiner, Chirag Sudarshan, Norbert Wehn, Lennart M. Reimann, Rainer Leupers, Michael Beyer, Daniel Khler, Alisa Jauch, Jan Micha Borrmann, Setareh Jaberansari, Tim Berthold, Meinolf Blawat, Markus Kock, Gregor Schewior, Jens Benndorf, Frederik Kautz, Hans-Martin Blthgen, Christian Sauer |
| 2023 | DATE | par-gem5: Parallelizing gem5's Atomic Mode. | Niko Zurstraen, Jos Cubero-Cascante, Jan Moritz Joseph, Li Yichao, Xinghua Xie, Rainer Leupers |
| 2023 | ICCD | Efficient RISC-V-on-x64 Floating Point Simulation. | Niko Zurstraen, Nils Bosbach, Jan Moritz Joseph, Lukas Jnger, Jan Henrik Weinstock, Rainer Leupers |
| 2022 | DAC | Designing ML-resilient locking at register-transfer level. | Dominik Sisejkovic, Luca Collini, Benjamin Tan, Christian Pilato, Ramesh Karri, Rainer Leupers |
| 2022 | DATE | NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future. | Melvin Galicia, Stephan Menzel, Farhad Merchant, Maximilian Mller, Hsin-Yu Chen, Qing-Tai Zhao, Felix Cppers, Abdur R. Jalil, Qi Shu, Peter Schffelgen, Gregor Mussler, Carsten Funck, Christian Lanius, Stefan Wiefels, Moritz von Witzleben, Christopher Bengel, Nils Kopperberg, Tobias Ziegler, R. Walied Ahmad, Alexander Krger, Letcia Maria Bolzani Phls, Regina Dittmann, Susanne Hoffmann-Eifert, Vikas Rana, Detlev Grtzmacher, Matthias Wuttig, Dirk J. Wouters, Andrei Vescan, Tobias Gemmeke, Joachim Knoch, Max Christian Lemme, Rainer Leupers, Rainer Waser |
| 2022 | DATE | NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. | Felix Staudigl, Hazem Al Indari, Daniel Schn, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers |
| 2022 | DSD | X-on-X: Distributed Parallel Virtual Platforms for Heterogeneous Systems. | Lukas Jnger, Simon Winther, Rainer Leupers |
| 2022 | FPL | EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs. | Yee Yang Tan, Felix Staudigl, Lukas Jnger, Anna Drewes, Rainer Leupers, Jan Moritz Joseph |
| 2021 | ASPDAC | Optimizing Temporal Decoupling using Event Relevance. | Lukas Jnger, Carmine Bianco, Kristof Niederholtmeyer, Dietmar Petras, Rainer Leupers |
| 2021 | ASPDAC | Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures. | Jan Moritz Joseph, Lennart Bamberg, Geonhwa Jeong, Ruei-Ting Chien, Rainer Leupers, Alberto Garca-Ortiz, Tushar Krishna, Thilo Pionteck |
| 2021 | DATE | Nano Security: From Nano-Electronics to Secure Systems. | Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Ralf Brederlow, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Gneysu, Sascha Hermann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer |
| 2021 | DSD | Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism. | Milan Copic, Rainer Leupers, Gerd Ascheid |
| 2021 | ICCD | QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. | Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers |
| 2021 | VLSID | An Investigation on Inherent Robustness of Posit Data Representation. | Ihsen Alouani, Anouar Ben Khalifa, Farhad Merchant, Rainer Leupers |
| 2021 | VLSID | ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. | Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers |
| 2020 | DATE | Next Generation Arithmetic for Edge Computing. | Andre Guntoro, Cecilia De la Parra, Farhad Merchant, Florent de Dinechin, John L. Gustafson, Martin Langhammer, Rainer Leupers, Sangeeth Nambiar |
| 2020 | DATE | ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual Platforms. | Lukas Jnger, Jan Luca Malte Blke, Stephan Tobies, Rainer Leupers, Andreas Hoffmann |
| 2020 | ISSRE | Modelling Machine Learning Components for Mapping and Scheduling of AUTOSAR Runnables. | Milan Copic, Rainer Leupers, Gerd Ascheid |
| 2020 | SCOPES | A secure hardware-software solution based on RISC-V, logic locking and microkernel. | Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Massimiliano Giacometti, Sascha Kegrei |
| 2019 | ASPDAC | Efficient sporadic task handling in parallel AUTOSAR applications using runnable migration. | Milan Copic, Rainer Leupers, Gerd Ascheid |
| 2019 | ASPDAC | A heuristic for multi objective software application mappings on heterogeneous MPSoCs. | Gereon Onnebrink, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Awaid-Ud-Din Shaheen |
| 2019 | ETS | Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries. | Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Sascha Kegreiss |
| 2019 | ISCAS | An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration. | Andreas Bytyn, Rainer Leupers, Gerd Ascheid |
| 2019 | VLSID | A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. | Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers |
| 2019 | VLSID | Applying Modified Householder Transform to Kalman Filter. | Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers |
| 2018 | DATE | OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation. | Robert Lajos Bcs, Maximilian Fricke, Rainer Leupers, Gerd Ascheid, Stephan Tobies, Andreas Hoffmann |
| 2018 | ICCD | Parameterized Posit Arithmetic Hardware Generator. | Rohit Chaurasiya, John L. Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi, Farhad Merchant, Rainer Leupers |
| 2018 | VEHITS | Fully Virtual Rapid ADAS Prototyping via a Joined Multi-domain Co-simulation Ecosystem. | Robert Lajos Bcs, Pramod Lakshman, Jan Henrik Weinstock, Florian Walbroel, Rainer Leupers, Gerd Ascheid |
| 2017 | CASES | Multi-grained performance estimation for MPSoC compilers: work-in-progress. | Miguel Angel Aguilar, Abhishek Aggarwal, Awaid Shaheen, Rainer Leupers, Gerd Ascheid, Jernimo Castrilln, Liam Fitzpatrick |
| 2017 | DATE | Schedule-aware loop parallelization for embedded MPSoCs by exploiting parallel slack. | Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Nikolaos Kavvadias, Liam Fitzpatrick |
| 2017 | ISCAS | VLSI implementation of LS-SVM training and classification using entropy based subset-selection. | Andreas Bytyn, Jannik Springer, Rainer Leupers, Gerd Ascheid |
| 2016 | DAC | Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs. | Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Luis Gabriel Murillo |
| 2016 | DATE | Mantissa-masking for energy-efficient floating-point LTE uplink MIMO baseband processing. | Daniel Gnther, Tomas Henriksson, Rainer Leupers, Gerd Ascheid |
| 2016 | DATE | Technology Transfer in computing systems: The TETRACOM approach. | Rainer Leupers |
| 2016 | DATE | SystemC-link: Parallel SystemC simulation using time-decoupled segments. | Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid, Dietmar Petras, Andreas Hoffmann |
| 2015 | ASPDAC | SWAT: Assertion-based debugging of concurrency issues at system level. | Luis Gabriel Murillo, Robert Lajos Bcs, Daniel Hincapie, Rainer Leupers, Gerd Ascheid |
| 2015 | DATE | Multi/many-core programming: where are we standing? | Jernimo Castrilln, Lothar Thiele, Lars Schor, Weihua Sheng, Ben H. H. Juurlink, Mauricio Alvarez-Mesa, Angela Pohl, Ralph Jessenberger, Victor Reyes, Rainer Leupers |
| 2015 | FDL | Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface. | Robert Lajos Bcs, Luis Gabriel Murillo, Ekaterina Korotcenko, Gaurav Dugge, Rainer Leupers, Gerd Ascheid, Andreas Ropers, Markus Wedler, Andreas Hoffmann |
| 2015 | HPCC | Extraction of Kahn Process Networks from While Loops in Embedded Software. | Miguel Angel Aguilar, Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Maximilian Odendahl |
| 2015 | PPoPP | A comparative investigation of device-specific mechanisms for exploiting HPC accelerators. | Ayman Tarakji, Lukas Brger, Rainer Leupers |
| 2015 | TrustCom | Enhanced GPU Resource Utilization through Fairness-aware Task Scheduling. | Ayman Tarakji, Alexander Gladis, Tarek Anwar, Rainer Leupers |
| 2015 | SCOPES | A Toolflow for Parallelization of Embedded Software in Multicore DSP Platforms. | Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Nikolaos Kavvadias |
| 2015 | SCOPES | Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation. | Juan Fernando Eusse, Luis Gabriel Murillo, Christopher McGirr, Rainer Leupers, Gerd Ascheid |
| 2015 | SCOPES | Modeling Exclusive Memory Access for a Time-Decoupled Parallel SystemC Simulator. | Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid |
| 2014 | DATE | A flexible ASIP architecture for connected components labeling in embedded vision applications. | Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Patrick Sudowe, Bastian Leibe, Tamon Sadasue |
| 2014 | DATE | Technology transfer towards Horizon 2020. | Rainer Leupers, Norbert Wehn, Marco Roodzant, Johannes Stahl, Luca Fanucci, Albert Cohen, Bernd Janson |
| 2014 | DATE | Automatic detection of concurrency bugs through event ordering constraints. | Luis Gabriel Murillo, Simon Wawroschek, Jernimo Castrilln, Rainer Leupers, Gerd Ascheid |
| 2014 | DATE | Optimized buffer allocation in multicore platforms. | Maximilian Odendahl, Andres Goens, Rainer Leupers, Gerd Ascheid, Benjamin Ries, Berthold Vcking, Tomas Henriksson |
| 2014 | DATE | Time-decoupled parallel SystemC simulation. | Jan Henrik Weinstock, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Laura Tosoratto |
| 2014 | IPCCC | A heuristic for logical data buffer allocation in multicore platforms. | Benjamin Ries, Walter Unger, Maximilian Odendahl, Rainer Leupers |
| 2014 | ISCAS | Efficient VLSI architectures for matrix inversion in soft-input soft-output MMSE MIMO detectors. | Dominik Auras, Rainer Leupers, Gerd Ascheid |
| 2014 | ISPA | EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems. | Lars Schor, Iuliana Bacivarov, Luis Gabriel Murillo, Pier Stanislao Paolucci, Frdric Rousseau, Ashraf El Antably, Robert Buecs, Nicolas Fournel, Rainer Leupers, Devendra Rai, Lothar Thiele, Laura Tosoratto, Piero Vicini, Jan Weinstock |
| 2014 | SCOPES | Improving ESL power models using switching activity information from timed functional models. | Stefan Schrmans, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Xiaotao Chen |
| 2013 | DAC | Creation of ESL power models for communication architectures using automatic calibration. | Stefan Schrmans, Diandian Zhang, Dominik Auras, Rainer Leupers, Gerd Ascheid, Xiaotao Chen, Lun Wang |
| 2013 | HPCC | Embedded Real-Time Application Prototyping Using a Hybrid Multiprocessing Platform. | Weihua Sheng, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid |
| 2013 | PPoPP | A compiler infrastructure for embedded heterogeneous MPSoCs. | Weihua Sheng, Stefan Schrmans, Maximilian Odendahl, Mark Bertsch, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid |
| 2012 | DAC | Communication-aware mapping of KPN applications onto heterogeneous MPSoCs. | Jernimo Castrilln, Andreas Tretter, Rainer Leupers, Gerd Ascheid |
| 2012 | DAC | Synchronization for hybrid MPSoC full-system simulation. | Luis Gabriel Murillo, Juan Fernando Eusse, Jovana Jovic, Sergey Yakoushkin, Rainer Leupers, Gerd Ascheid |
| 2012 | DATE | Hybrid simulation for extensible processor cores. | Jovana Jovic, Sergey Yakoushkin, Luis Gabriel Murillo, Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid |
| 2012 | DATE | Virtual platforms: Breaking new grounds. | Rainer Leupers, Grant Martin, Roman Plyaskin, Andreas Herkersdorf, Frank Schirrmeister, Tim Kogel, Martin Vaupel |
| 2012 | FDL | Scandal: Systemc analysis for nondeterminism anomalies. | Christoph Schumacher, Jan Weinstock, Rainer Leupers, Gerd Ascheid |
| 2012 | FDL | SCandal: SystemC Analysis for Nondeterminism Anomalies. | Jan Henrik Weinstock, Christoph Schumacher, Rainer Leupers, Gerd Ascheid |
| 2011 | DATE | Virtual Manycore platforms: Moving towards 100+ processor cores. | Rainer Leupers, Lieven Eeckhout, Grant Martin, Frank Schirrmeister, Nigel P. Topham, Xiaotao Chen |
| 2011 | SCOPES | Enhanced structural analysis for C code reconstruction from IR code. | Felix Engel, Rainer Leupers, Gerd Ascheid, Max Ferger, Marcel Beemster |
| 2010 | ASPDAC | MPSoC programming using the MAPS compiler. | Rainer Leupers, Jernimo Castrilln |
| 2010 | DATE | Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. | Jernimo Castrilln, Ricardo Velasquez, Anastasia Stulova, Weihua Sheng, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
| 2010 | DATE | Cool MPSoC programming. | Rainer Leupers, Lothar Thiele, Xiaoning Nie, Bart Kienhuis, Matthias Weiss, Tsuyoshi Isshiki |
| 2010 | SCOPES | System level MPSoC design: a bright future for compiler technology? | Rainer Leupers |
| 2009 | DATE | Programming MPSoC platforms: Road works ahead! | Rainer Leupers, Andras Vajda, Marco Bekooij, Soonhoi Ha, Rainer Dmer, Achim Nohl |
| 2009 | ICCAD | Task management in MPSoCs: An ASIP approach. | Jernimo Castrilln, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid |
| 2009 | VLSID | A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. | Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr |
| 2008 | DAC | MAPS: an integrated framework for MPSoC application parallelization. | Jianjiang Ceng, Jernimo Castrilln, Weihua Sheng, Hanno Scharwchter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda |
| 2008 | DAC | Multiprocessor performance estimation using hybrid simulation. | Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
| 2008 | DATE | High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. | Anupam Chattopadhyay, Xiaolin Chen, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
| 2008 | DATE | Retargetable Code Optimization for Predicated Execution. | Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh |
| 2008 | DATE | System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures. | Rainer Leupers, Gerd Ascheid, Wilfried Verachtert, Tom Ashby, Arnout Vandecappelle |
| 2007 | CASES | A fast and generic hybrid simulation approach using C virtual machine. | Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
| 2007 | DATE | Design space exploration of partially re-configurable embedded processors. | Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
| 2007 | DATE | Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations. | Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
| 2007 | ICCAD | Increasing data-bandwidth to instruction-set extensions through register clustering. | Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
| 2007 | RSP | Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. | Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
| 2006 | DATE | An integrated open framework for heterogeneous MPSoC design space exploration. | Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini |
| 2006 | DATE | Automatic ADL-based operand isolation for embedded processors. | Anupam Chattopadhyay, Benedikt Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
| 2006 | DATE | ASIP design and synthesis for non linear filtering in image processing. | Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr |
| 2006 | DATE | Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. | Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia |
| 2006 | DATE | A SW performance estimation framework for early system-level-design using fine-grained instrumentation. | Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr |
| 2006 | DATE | A design flow for configurable embedded processors based on optimized instruction set extension synthesis. | Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, Manas Pandey |
| 2006 | DATE | An interprocedural code optimization technique for network processors using hardware multi-threading support. | Hanno Scharwchter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
| 2006 | RSP | Integrated Verification Approach during ADL-Driven Processor Design. | Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
| 2005 | ASPDAC | A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. | Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel |
| 2005 | DAC | Fine-grained application source code profiling for ASIP design. | Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
| 2005 | DATE | C Compiler Retargeting Based on Instruction Semantics Models. | Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun |
| 2005 | DATE | A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. | Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout |
| 2005 | RSP | Optimization Techniques for ADL-Driven RTL Processor Synthesis. | Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr |
| 2004 | ASPDAC | Compiler based exploration of DSP energy savings by SIMD operations. | Markus Lorenz, Peter Marwedel, Thorsten Drger, Gerhard P. Fettweis, Rainer Leupers |
| 2004 | DAC | A novel approach for flexible and consistent ADL-driven ASIP design. | Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwchter, Rainer Leupers, Heinrich Meyr |
| 2004 | DATE | A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. | Manuel Hohenauer, Hanno Scharwchter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren |
| 2004 | DATE | RTL Processor Synthesis for Architecture Exploration and Implementation. | Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl |
| 2004 | DATE | A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. | Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl |
| 2004 | SCOPES | ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. | Hanno Scharwchter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
| 2003 | CC | Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms. | Rainer Leupers |
| 2003 | DAC | Instruction encoding synthesis for architecture exploration using hierarchical processor models. | Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr |
| 2003 | DATE | Processor/Memory Co-Exploration on Multiple Abstraction Levels. | Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl |
| 2003 | SCOPES | Improving Offset Assignment through Simultaneous Variable Coalescing. | Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers |
| 2003 | SCOPES | Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. | Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie |
| 2002 | DAC | A universal technique for fast and flexible instruction-set architecture simulation. | Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann |
| 2001 | ASPDAC | Optimized address assignment for DSPs with SIMD memory accesses. | Markus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel |
| 2001 | ICASSP | Variable partitioning for dual memory bank DSPs. | Rainer Leupers, Daniel Kotte |
| 2001 | ICCD | Low-Energy DSP Code Generation Using a Genetic Algorithm. | Markus Lorenz, Rainer Leupers, Peter Marwedel, Thorsten Drger, Gerhard P. Fettweis |
| 2001 | PLDI | C Compiler Design for an Industrial Network Processor. | Jens Wagner, Rainer Leupers |
| 2000 | ASPDAC | Register allocation for common subexpressions in DSP data paths. | Rainer Leupers |
| 2000 | DATE | Code Selection for Media Processors with SIMD Instructions. | Rainer Leupers |
| 1999 | ASPDAC | Generation of Interpretive and Compiled Instruction Set Simulators. | Rainer Leupers, Johann Elste, Birger Landwehr |
| 1999 | DAC | Constraint Driven Code Selection for Fixed-Point DSPs. | Steven Bashford, Rainer Leupers |
| 1999 | DATE | Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors. | Rainer Leupers |
| 1999 | ICCAD | Function inlining under code size constraints for embedded processors. | Rainer Leupers, Peter Marwedel |
| 1999 | VLSID | Array Index Allocation under Register Constraints in DSP Programs. | Anupam Basu, Rainer Leupers, Peter Marwedel |
| 1998 | ASPDAC | Optimized Array Index Computation in DSP Programs. | Rainer Leupers, Anupam Basu, Peter Marwedel |
| 1998 | DATE | Register-Constrained Address Computation in DSP Programs. | Anupam Basu, Rainer Leupers, Peter Marwedel |
| 1997 | DATE | Retargetable generation of code selectors from HDL processor models. | Rainer Leupers, Peter Marwedel |
| 1996 | ICCAD | Algorithms for address assignment in DSP code generation. | Rainer Leupers, Peter Marwedel |
| 1996 | VLSID | Instruction-Set Modeling for ASIP Code Generation. | Rainer Leupers, Peter Marwedel |
| 1995 | DATE | A BDD-based frontend for retargetable compilers. | Rainer Leupers, Peter Marwedel |
| 1993 | DAC | Resistance Extraction using a Routing Algorithm. | Lorenz Ladage, Rainer Leupers |