FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study.
Helena Krupnova, Christian Rabedaoro, Gabriele Saucier
VenueCRSP
Year1999
ProceedingsIEEE International Workshop on Rapid System Prototyping
DBLP recordconf/rsp/KrupnovaRS99 ↗
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