| 2002 | DATE | Who Owns the Platform? | Vassilios Gerousis, Oz Levia, Pierre G. Paulin, Mark Pinto, Chris Rowen, Gabriele Saucier |
| 2002 | DATE | E-Design Based on the Reuse Paradigm. | L. Ghanmi, A. Ghrab, M. Hamdoun, B. Missaoui, K. Skiba, Gabriele Saucier |
| 2000 | FPL | FPGA-Based Emulation: Industrial and Custom Prototyping Solutions. | Helena Krupnova, Gabriele Saucier |
| 2000 | RSP | FPGA Technology Snapshot: Current Devices and Design Tools. | Helena Krupnova, Gabriele Saucier |
| 1999 | DATE | Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs. | Helena Krupnova, Gabriele Saucier |
| 1999 | FPGA | Partitioning Large Designs by Filling PFGA Devices with Hierarchy Blocks. | Helena Krupnova, Gabriele Saucier |
| 1999 | FPL | Hierarchical Interactive Approach to Partition Large Designs into FPGAs. | Helena Krupnova, Gabriele Saucier |
| 1999 | RSP | FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study. | Helena Krupnova, Christian Rabedaoro, Gabriele Saucier |
| 1998 | FPGA | Block and IP Wrapping for Efficient Design on FPGAs (Abstract). | Helena Krupnova, B. Behnam, Gabriele Saucier |
| 1998 | FPGA | Timing Driven Floorplanning on Programmable Hierarchical Targets. | S. A. Senouci, Aadil Amoura, Helena Krupnova, Gabriele Saucier |
| 1998 | FPL | A Knowledge-Based System for Prototyping on FPFAs. | Helena Krupnova, Vu DucAnh Dinh, Gabriele Saucier |
| 1998 | VLSID | Fast Arithmetic on Xilinx 5200 FPGA. | Bernard Laurent, Gilles Bosco, Gabriele Saucier |
| 1998 | RSP | Real Time Prototyping Method and a Case Study. | Helena Krupnova, Dinh Duc Anh Vu, Gabriele Saucier, Michel Boubal |
| 1997 | DAC | A Hierarchy-Driven FPGA Partitioning Method. | Helena Krupnova, Ali Abbara, Gabriele Saucier |
| 1997 | FPGA | Synthesis and Floorplanning for Large Hierarchical FPGAs. | Helena Krupnova, Christian Rabedaoro, Gabriele Saucier |
| 1997 | FPL | Structural versus algorithmic approaches for efficient adders on Xilinx 5200 FPGA. | Bernard Laurent, Gilles Bosco, Gabriele Saucier |
| 1995 | DATE | Efficient synthesis of fault-tolerant controllers. | Raphal Rochet, Rgis Leveugle, Gabriele Saucier |
| 1994 | DAC | Design Automation Tools for FPGA Design (Panel). | Kella Knack, Gordan Hyland, Jim Jasmin, John Frediani, Tom Reiner, Steven Trimberger, Gabriele Saucier |
| 1993 | ICCAD | Partitioning with cone structures. | Gabriele Saucier, Daniel R. Brasen, J. P. Hiol |
| 1993 | ICCD | Influence of Error Correlations on the Signature Analysis Aliasing. | Rgis Leveugle, X. Delord, Gabriele Saucier |
| 1992 | ICCD | Synthesis on Multiplexer-Based F.P.G.A. Using Binary Decision Diagrams. | T. Besson, H. Bouzouzou, M. Crastes, Ion Floricica, Gabriele Saucier |
| 1991 | DAC | A Technology Mapping Method Based On Perfect And Semi-Perfect Matchings. | M. Crastes, K. Sakouti, Gabriele Saucier |
| 1991 | ICCAD | State Assignment Based on the Reduced Dependency Theory and Recent Experimental Results. | Christopher Duff, Gabriele Saucier |
| 1991 | ITC | Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Multiprocessors. | X. Delord, Gabriele Saucier |
| 1991 | ITC | Hierarchical Test Generation Based on Delayed Propagation. | Margot Karam, Rgis Leveugle, Gabriele Saucier |
| 1990 | DAC | Multilevel Synthesis Minimizing the Routing Factor. | Pierre Abouzeid, K. Sakouti, Gabriele Saucier, Franck Poirot |
| 1990 | IJCNN | Silicon compiler for neuro-ASICs. | J. Ouali, Gabriele Saucier |
| 1989 | DAC | State Assignment Using a New Embedding Method Based on an Intersecting Cube Theory. | Gabriele Saucier, Christopher Duff, Franck Poirot |
| 1989 | ICCD | Concurrent checking in dedicated controllers. | Rgis Leveugle, Gabriele Saucier |
| 1989 | ICCD | A flexible architecture for neural networks. | J. Ouali, Gabriele Saucier |
| 1989 | ICCD | A channelless layout for multilevel synthesis with compiled cells. | Gabriele Saucier, Rgis Leveugle, Pierre Abouzeid |
| 1989 | ITC | Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. | Rgis Leveugle, Gabriele Saucier |
| 1989 | ITC | Testability Expertise and Test Planning from High-Level Specifications. | Michel Crastes de Paulet, Margot Karam, Gabriele Saucier |
| 1988 | GI | Entwurf eines systolischen Arrays in Wafer Scale Technik fr die digitale Signalverarbeitung. | Manfred Glesner, M. Huch, Peter A. Ivey, T. Midwinter, Gabriele Saucier, Jacques Trilhe |
| 1987 | DAC | An Application of Exploratory Data Analysis Techniques to Floorplan Design. | E. F. M. Kouka, Gabriele Saucier |
| 1985 | DAC | Systematic and optimized layout of MOS cells. | Gabriele Saucier, Ghislaine Thuau |
| 1984 | DAC | VLSI test expertise system using a control flow model. | Gabriele Saucier, Catherine Bellon |
| 1984 | ITC | CADOC : A System for Computer Aided Functional Test. | Catherine Bellon, Gabriele Saucier |
| 1982 | DAC | Top down design and testability of VLSI circuits. | Philippe Basset, Gabriele Saucier |
| 1982 | DAC | Automatic generation of microprocessor test programs. | Catherine Bellon, A. Liothin, Sylvain Sadier, Gabriele Saucier, Raoul Velazco, Francois Grillot, M. Issenman |
| 1981 | DAC | Hardware description levels and test for complex circuits. | Catherine Bellon, Gabriele Saucier, Jos-Maria Gobbi |
| 1976 | ISCA | A Design Tool for the Multilevel Description and Simulation of Systems of Interconnected Modules. | M. Moalla, Gabriele Saucier, Joseph Sifakis, Marianthi Zachariades |
| 1975 | MICRO | On balancing hardware-firmware for designing a fault-tolerant computers' series. | Bernard Courtois, Gabriele Saucier |