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Paper
Floorplanning for Partial Reconfiguration in FPGAs.
Pritha Banerjee
,
Megha Sangtani
,
Susmita Sur-Kolay
Venue
National
VLSID
Year
2009
Proceedings
VLSI Design
DBLP record
conf/vlsid/BanerjeeSS09 ↗
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