| 2025 | VLSID | Constructing Rectilinear Steiner Minimum Tree with Conditional Generative Adversarial Network. | Kritanta Saha, Pritha Banerjee, Susmita Sur-Kolay |
| 2024 | VLSID | Optimized QAOA ansatz circuit design for two-body Hamiltonian problems. | Ritajit Majumdar, Dhiraj Madan, Debasmita Bhoumik, Dhinakaran Vinayagamurthy, Shesha Raghunathan, Susmita Sur-Kolay |
| 2022 | ITC | GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs. | Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay |
| 2022 | VLSID | Stitch-avoiding Global Routing for Multiple E-Beam Lithography. | Kritanta Saha, Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay |
| 2021 | IVCNZ | 3D Reconstruction from Micro-CT Slices for Non-Destructive Viewing inside a Fossil. | Somoballi Ghoshal, Partha Bhowmick, Amlan Chakrabarti, Susmita Sur-Kolay, Sanjukta Chakravorti, Dhurjati Sengupta |
| 2020 | ICCD | Special Session: Quantum Error Correction in Near Term Systems. | Ritajit Majumdar, Susmita Sur-Kolay |
| 2019 | VLSID | Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays. | Manobennath Mondal, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
| 2017 | ICCD | Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography. | Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay |
| 2017 | RC | A Method to Reduce Resources for Quantum Error Correction. | Ritajit Majumdar, Saikat Basu, Susmita Sur-Kolay |
| 2017 | VLSID | Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICs. | Debasri Saha, Susmita Sur-Kolay |
| 2016 | ISCAS | An efficient synthesis method for ternary reversible logic. | Saikat Basu, Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay |
| 2016 | VLSID | A Novel EPE Aware Hybrid Global Route Planner after Floorplanning. | Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal |
| 2014 | CASES | Trusted sharing of intellectual property in electronic hardware design. | Debasri Saha, Susmita Sur-Kolay |
| 2014 | ICDCIT | Energy-Aware H.264 Decoding. | Arani Bhattacharya, Ansuman Banerjee, Susmita Sur-Kolay |
| 2014 | VLSID | Global Routing Using Monotone Staircases with Minimal Bends. | Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal |
| 2012 | VLSID | Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design. | Susmita Sur-Kolay, Swarup Bhunia |
| 2010 | VLSID | A Unified Approach for IP Protection across Design Phases in a Packaged Chip. | Debasri Saha, Susmita Sur-Kolay |
| 2009 | VLSID | Floorplanning for Partial Reconfiguration in FPGAs. | Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay |
| 2009 | VLSID | Encoding of Floorplans through Deterministic Perturbation. | Debasri Saha, Susmita Sur-Kolay |
| 2007 | CIT | Fast Robust Intellectual Property Protection for VLSI Physical Design. | Debasri Saha, Susmita Sur-Kolay |
| 2007 | VLSID | Floorplanning in Modern FPGAs. | Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu |
| 2006 | CIT | Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI. | Sriparna Saha, Susmita Sur-Kolay, Sanghamitra Bandyopadhyay, Parthasarathi Dasgupta |
| 2006 | VLSID | Test Pattern Generation for Power Supply Droop Faults. | Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu |
| 2005 | FPL | Fast FPGA Placement using Space-filling Curve. | Pritha Banerjee, Subhasis Bhattacharjee, Susmita Sur-Kolay, Sandip Das, Subhas C. Nandy |
| 2005 | VLSID | Hot Spots and Zones in a Chip: A Geometrician's View. | Subhashis Majumder, Susmita Sur-Kolay, Subhas C. Nandy, Bhargab B. Bhattacharya, B. Chakraborty |
| 2004 | DATE | A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. | Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang |
| 2004 | VLSID | Physical Design Trends and Layout-Based Fault Modeling. | Susmita Sur-Kolay, Parthasarathi Dasgupta, Bhargab B. Bhattacharya, Sujit T. Zachariah |
| 2001 | FCCM | Combining Instruction and Loop Level Parallelism for FPGAs. | Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay |
| 2001 | ISCAS | Area(number)-balanced hierarchy of staircase channels with minimum crossing nets. | Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Subhas C. Nandy |
| 2001 | VLSID | Partitioning Routing Area into Zones with Distinct Pins. | Koushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhattacharya, P. S. Dasgupta |
| 2000 | VLSID | Topological Routing Amidst Polygonal Obstacles. | Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
| 1998 | VLSID | Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model. | Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
| 1995 | ICCAD | A unified approach to topology generation and area optimization of general floorplans. | Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
| 1995 | VLSID | VLSI floorplan generation and area optimization using AND-OR graph search. | P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
| 1992 | DAC | Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning. | Susmita Sur-Kolay, Bhargab B. Bhattacharya |
| 1991 | ICCD | The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order. | Susmita Sur-Kolay, Bhargab B. Bhattacharya |