40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode.

Kedar Janardan Dhori, Promod Kumar, Christophe Lecocq, Pascal Urard, Olivier Callen, Florian Cacho, Maryline Parra, Prashant Pandey, Daniel Noblet

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