A Power Minimization Technique for Arithmetic Circuits by Cell Selection.
Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura
Browse the full VLSID paper archive.
Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura
Browse the full VLSID paper archive.