| 2023 | DATE | An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits. | Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara |
| 2023 | IOLTS | Feedback-Tuned Fuzzing for Accelerating Quality Verification of Approximate Computing Design. | Yusei Honda, Yutaka Masuda, Tohru Ishihara |
| 2022 | ASPDAC | An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers. | Lingxiao Hou, Yutaka Masuda, Tohru Ishihara |
| 2022 | DAC | Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design. | Naoki Hattori, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi |
| 2022 | RTCSA | DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms. | Takumi Komori, Yutaka Masuda, Tohru Ishihara |
| 2021 | DATE | Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design. | Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto |
| 2021 | IOLTS | Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing. | Kazuki Yoshisue, Yutaka Masuda, Tohru Ishihara |
| 2019 | ASPDAC | BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing. | Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi |
| 2019 | SC | An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator. | Tohru Ishihara, Jun Shiomi, Naoki Hattori, Yutaka Masuda, Akihiko Shinya, Masaya Notomi |
| 2018 | IOLTS | Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation. | Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera |
| 2016 | ASPDAC | A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. | Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera |
| 2015 | ASPDAC | Microarchitectural-level statistical timing models for near-threshold circuit design. | Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera |
| 2012 | ICCD | A flexible structure of standard cell and its optimization method for near-threshold voltage operation. | Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera |
| 2011 | DATE | Developing an integrated verification and debug methodology. | Akitoshi Matsuda, Tohru Ishihara |
| 2011 | ISLPED | An integrated optimization framework for reducing the energy consumption of embedded real-time applications. | Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Shunitsu Kohara, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada |
| 2010 | CASES | Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems. | Lovic Gauthier, Tohru Ishihara, Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada |
| 2008 | EUC | A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems. | Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Tohru Ishihara |
| 2008 | ISLPED | Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation. | Maziar Goudarzi, Tohru Ishihara |
| 2007 | ASPDAC | A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. | Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura |
| 2007 | DATE | Task scheduling for reliable cache architectures of multiprocessor systems. | Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami |
| 2005 | DATE | A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors. | Tohru Ishihara, Farzan Fallah |
| 2005 | ICCAD | A cache-defect-aware code placement algorithm for improving the performance of processors. | Tohru Ishihara, Farzan Fallah |
| 2005 | ISLPED | A non-uniform cache architecture for low power system design. | Tohru Ishihara, Farzan Fallah |
| 2002 | VLSID | An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. | Tohru Ishihara, Kunihiro Asada |
| 2002 | VLSID | A Power Minimization Technique for Arithmetic Circuits by Cell Selection. | Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura |
| 2001 | ASPDAC | A system level memory power optimization technique using multiple supply and threshold voltages. | Tohru Ishihara, Kunihiro Asada |
| 2000 | DATE | A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. | Tohru Ishihara, Hiroto Yasuura |
| 1999 | ISLPED | Way-predicting set-associative cache for high performance and low energy consumption. | Koji Inoue, Tohru Ishihara, Kazuaki J. Murakami |
| 1998 | ASPDAC | Power-Pro: Programmable Power Management Architecture. | Tohru Ishihara, Hiroto Yasuura |
| 1998 | DATE | Instruction Scheduling for Power Reduction in Processor-Based System Design. | Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura |
| 1998 | ISLPED | Voltage scheduling problem for dynamically variable voltage processors. | Tohru Ishihara, Hiroto Yasuura |
| 1996 | ISLPED | Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. | Tohru Ishihara, Hiroto Yasuura |