Skip to content
cs-conference-ranking
.org
By subfield
By rank
Methodology
⌕
Search 971 venues
Home
/
VLSID
/
Paper
Optimal Clock Period for Synthesized Data Paths.
A. R. Naseer
,
M. Balakrishnan
,
Anshul Kumar
Venue
National
VLSID
Year
1997
Proceedings
VLSI Design
DBLP record
conf/vlsid/NaseerBK97 ↗
Browse the full
VLSID paper archive
.