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Recent Advances in Verification, Equivalence Checking and SAT-Solvers.
Dhiraj K. Pradhan
,
Magdy S. Abadir
,
Mauricio Varea
Venue
National
VLSID
Year
2005
Proceedings
VLSI Design
DBLP record
conf/vlsid/PradhanAV05 ↗
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