| 2014 | DAC | Data Mining In EDA - Basic Principles, Promises, and Constraints. | Li-C. Wang, Magdy S. Abadir |
| 2014 | IOLTS | Multivariate outlier modeling for capturing customer returns - How simple it can be. | Jeff Tikkanen, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir |
| 2014 | ITC | Yield optimization using advanced statistical correlation methods. | Jeff Tikkanen, Sebastian Siatkowski, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir |
| 2013 | DAC | Simulation knowledge extraction and reuse in constrained random processor verification. | Wen Chen, Li-C. Wang, Jay Bhadra, Magdy S. Abadir |
| 2013 | ITC | A pattern mining framework for inter-wafer abnormality analysis. | Nik Sumikawa, Li-C. Wang, Magdy S. Abadir |
| 2012 | ICCAD | Novel test detection to improve simulation efficiency - A commercial experiment. | Wen Chen, Nik Sumikawa, Li-C. Wang, Jayanta Bhadra, Xiushan Feng, Magdy S. Abadir |
| 2012 | ITC | Screening customer returns with multivariate test analysis. | Nik Sumikawa, Jeff Tikkanen, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir |
| 2012 | ITC | An experiment of burn-in time reduction based on parametric test analysis. | Nik Sumikawa, Li-C. Wang, Magdy S. Abadir |
| 2011 | DATE | Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits. | Dragoljub Gagi Drmanac, Nik Sumikawa, LeRoy Winemberg, Li-C. Wang, Magdy S. Abadir |
| 2011 | ITC | Forward prediction based on wafer sort data - A case study. | Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir |
| 2011 | VTS | Understanding customer returns from a test perspective. | Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir |
| 2010 | DAC | Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch. | Nicholas Callegari, Dragoljub Gagi Drmanac, Li-C. Wang, Magdy S. Abadir |
| 2009 | DATE | TRAM: A tool for Temperature and Reliability Aware Memory Design. | Amin Khajeh, Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Ahmed M. Eltawil, Kamal S. Khouri, Magdy S. Abadir |
| 2009 | ITC | Minimizing outlier delay test cost in the presence of systematic variability. | Dragoljub Gagi Drmanac, Brendon Bolin, Li-C. Wang, Magdy S. Abadir |
| 2008 | DAC | Statistical diagnosis of unmodeled systematic timing effects. | Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir |
| 2008 | DAC | Predictive runtime verification of multi-processor SoCs in SystemC. | Alper Sen, Vinit Ogale, Magdy S. Abadir |
| 2008 | ITC | Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained. | Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir |
| 2007 | ASPDAC | LEAF: A System Level Leakage-Aware Floorplanner for SoCs. | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
| 2007 | DAC | Design-Silicon Timing Correlation A Data Mining Perspective. | Li-C. Wang, Pouria Bastani, Magdy S. Abadir |
| 2007 | DATE | Maximum circuit activity estimation using pseudo-boolean satisfiability. | Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir |
| 2007 | ITC | Analyzing the risk of timing modeling based on path delay tests. | Pouria Bastani, Benjamin N. Lee, Li-C. Wang, Savithri Sundareswaran, Magdy S. Abadir |
| 2007 | ITC | Statistical analysis and optimization of parametric delay test. | Sean Hsi Yuan Wu, Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir |
| 2007 | VLSID | STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
| 2006 | DAC | Refined statistical static timing analysis through. | Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir |
| 2006 | IOLTS | Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs. | Magdy S. Abadir |
| 2006 | ITC | Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical Perspective. | Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir |
| 2005 | DAC | Choosing flows and methodologies for SoC design. | Dennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris |
| 2005 | ICCAD | Post-verification debugging of hierarchical designs. | Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler |
| 2005 | ITC | Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defects. | Benjamin N. Lee, Hui Li, Li-C. Wang, Magdy S. Abadir |
| 2005 | VLSID | Recent Advances in Verification, Equivalence Checking and SAT-Solvers. | Dhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea |
| 2005 | VTS | Reducing Pattern Delay Variations for Screening Frequency Dependent Defects. | Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir |
| 2004 | DAC | On path-based learning and its applications in delay test and diagnosis. | Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir |
| 2004 | ICCAD | Debugging sequential circuits using Boolean satisfiability. | Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir |
| 2004 | ISCAS | Fault equivalence and diagnostic test generation using ATPG. | Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Mandana Amiri |
| 2004 | ITC | On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. | Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham |
| 2004 | VLSID | Towards The Complete Elimination of Gate/Switch Level Simulations. | Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham |
| 2003 | ASPDAC | Enhanced symbolic simulation for efficient verification of embedded array systems. | Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Manish Pandey, Magdy S. Abadir |
| 2003 | ASPDAC | An automated method for test model generation from switch level circuits. | Tim McDougall, Atanas N. Parashkevov, Simon Jolly, Juhong Zhu, Jing Zeng, Carol Pyron, Magdy S. Abadir |
| 2003 | ASPDAC | Logic verification based on diagnosis techniques. | Andreas G. Veneris, Alexander Smith, Magdy S. Abadir |
| 2003 | DATE | Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. | Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir |
| 2003 | ICCAD | IDAP: A Tool for High Level Power Estimation of Custom Array Structures. | Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir |
| 2003 | ITC | Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. | Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir |
| 2003 | VTS | Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs. | Magdy S. Abadir, Juhong Zhu |
| 2002 | DAC | False timing path identification using ATPG techniques and delay-based information. | Jing Zeng, Magdy S. Abadir, Jacob A. Abraham |
| 2002 | DATE | Minimal Test for Coupling Faults in Word-Oriented Memories. | Ad J. van de Goor, Magdy S. Abadir, Alan Carlin |
| 2002 | DATE | Incremental Diagnosis and Correction of Multiple Faults and Errors. | Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir |
| 2002 | ITC | Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. | Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir |
| 2002 | ITC | Design Rewiring Using ATPG. | Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri |
| 2002 | ITC | On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults. | Li-C. Wang, Magdy S. Abadir, Juhong Zhu |
| 2002 | VTS | Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? | Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham |
| 2001 | ASPDAC | Design rewiring based on diagnosis techniques. | Andreas G. Veneris, Magdy S. Abadir, Ivor Ting |
| 2001 | DATE | Full chip false timing path identification: applications to the PowerPCTM microprocessors. | Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham |
| 2001 | IOLTS | Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. | Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir |
| 2001 | VTS | ATPG for Design Errors-Is It Possible? | Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma |
| 2001 | VTS | Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor. | Magdy S. Abadir, Juhong Zhu, Li-C. Wang |
| 2000 | VTS | Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. | Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham |
| 1999 | ITC | Design-for-test methodology for Motorola PowerPC microprocessors. | Magdy S. Abadir, Rajesh Raina |
| 1999 | ITC | Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors. | Li-C. Wang, Magdy S. Abadir |
| 1998 | DAC | Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation. | Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy |
| 1998 | DATE | Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays. | Li-C. Wang, Magdy S. Abadir, Jing Zeng |
| 1998 | VTS | On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays. | Li-C. Wang, Magdy S. Abadir, Jing Zeng |
| 1997 | DAC | Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation. | Manish Pandey, Richard Raimi, Randal E. Bryant, Magdy S. Abadir |
| 1997 | ITC | A New Validation Methodology Combining Test and Formal Verification for PowerPC | Li-C. Wang, Magdy S. Abadir |
| 1997 | VTS | Microprocessor Test and Validation: Any New Avenues? | Magdy S. Abadir, Jacob A. Abraham, Hong Hao, C. Hunter, Wayne M. Needham, Ron G. Walther |
| 1996 | ITC | PowerPC | Neeta Ganguly, Magdy S. Abadir, Manish Pandey |
| 1993 | ICCD | AMBIANT: Automatic Generation of Behavioral Modifications for Testability. | Praveen Vishakantaiah, Thomas Thomas, Jacob A. Abraham, Magdy S. Abadir |
| 1992 | DAC | Automatic Test Knowledge Extraction from VHDL (ATKET). | Praveen Vishakantaiah, Jacob A. Abraham, Magdy S. Abadir |
| 1991 | ITC | Partitioning Hierarchical Designs for Testability. | Magdy S. Abadir, Joe Newman, Desmond D'Souza, Steve Spencer |
| 1989 | ICCAD | TIGER: testability insertion guidance expert system. | Magdy S. Abadir |
| 1986 | ITC | Scan Path with Look Ahead Shifting (SPLASH). | Magdy S. Abadir, Melvin A. Breuer |
| 1985 | ITC | Functional Test Generation for LSI Circuits Described by Binary Decision Diagrams. | Magdy S. Abadir, Hassan K. Reghbati |
| 1984 | DAC | Test generation for LSI: A case study. | Magdy S. Abadir, Hassan K. Reghbati |