Skip to content
cs-conference-ranking
.org
By subfield
By rank
Methodology
⌕
Search 971 venues
Home
/
VLSID
/
Paper
Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design.
Sreeranga P. Rajan
,
Masahiro Fujita
Venue
National
VLSID
Year
1998
Proceedings
VLSI Design
DBLP record
conf/vlsid/RajanF98 ↗
Browse the full
VLSID paper archive
.