An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect.
Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu
Browse the full VLSID paper archive.
Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu
Browse the full VLSID paper archive.