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Sandip Kundu

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

100

Venues

17

Active years

1988–2026

Best venue rank

A*

Where they publish

Papers

100 indexed papers, newest first.

YearVenueTitleAuthors
2026VLSIDThermal Runaway Analysis of Analog PIM Accelerators.Huatao Wu, Sandip Kundu
2025VLSIDA Study on Efficiency Improvements of DNN Accelerators via Denormalized Arithmetic Elimination.Alexander Kharitonov, Sandip Kundu
2024DATEMemory Scraping Attack on Xilinx FPGAs: Private Data Extraction from Terminated Processes.Bharadwaj Madabhushi, Sandip Kundu, Daniel E. Holcomb
2023DATEA Novel Fault-Tolerant Architecture for Tiled Matrix Multiplication.Sandeep Bal, Chandra Sekhar Mummidi, Victor da Cruz Ferreira, Sudarshan Srinivasan, Sandip Kundu
2022ICCDA Highly-Efficient Error Detection Technique for General Matrix Multiplication using Tiled Processing on SIMD Architecture.Chandra Sekhar Mummidi, Sandeep Bal, Brunno F. Goldstein, Sudarshan Srinivasan, Sandip Kundu
2022IOLTSA Software Approach Towards Defeating Power Management Side Channel Leakage.Md. Nazmul Islam, Sandip Kundu
2022VTCReinforcement Learning based Multi-Attribute Slice Admission Control for Next-Generation Networks in a Dynamic Pricing Environment.Victor da Cruz Ferreira, Haitham H. Esmat, Beatriz Lorenzo, Sandip Kundu, Felipe M. G. Frana
2021DSNMILR: Mathematically Induced Layer Recovery for Plaintext Space Error Correction of CNNs.Jonathan Ponader, Kyle Thomas, Sandip Kundu, Yan Solihin
2020ESANNTowards Adversarial Attack Resistant Deep Neural Networks.Tiago A. O. Alves, Sandip Kundu
2020IOLTSReduced Fault Coverage as a Target for Design Scaffolding Security.Irith Pomeranz, Sandip Kundu
2019DASCHardware-Accelerated Similarity Search with Multi-Index Hashing.Leandro Santiago de Arajo, Victor da Cruz Ferreira, Brunno Figueiroa Goldstein, Alexandre Solon Nery, Leandro Augusto Justen Marzulo, Sandip Kundu, Felipe Maia Galvo Frana
2019ESANNMemory Efficient Weightless Neural Network using Bloom Filter.Leandro Santiago de Arajo, Letcia Dias Verona, Fbio Medeiros Rangel, Fabrcio Firmino de Faria, Daniel Sadoc Menasch, Wouter Caarls, Maurcio Breternitz, Sandip Kundu, Priscila Machado Vieira Lima, Felipe Maia Galvo Frana
2018ASPDACPMU-Trojan: On exploiting power management side channel for information leakage.Md. Nazmul Islam, Sandip Kundu
2017ISCASA guide to graceful aging: How not to overindulge in post-silicon burn-in for enhancing reliability of weak PUF.Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu
2017VTSAn analytical model for predicting the residual life of an IC and design of residual-life meter.Md. Nazmul Islam, Sandip Kundu
2016ICCDImproving performance per Watt of non-monotonic Multicore Processors via bottleneck-based online program phase classification.Sudarshan Srinivasan, Israel Koren, Sandip Kundu
2016VLSIDEfficient Error-Detection and Recovery Mechanisms for Reliability and Resiliency of Multicores.Sandip Kundu, Omer Khan
2016VLSIDDynamic Reconfiguration vs. DVFS: A Comparative Study on Power Efficiency of Processors.Sudarshan Srinivasan, Nithesh Kurella, Israel Koren, Sandip Kundu
2016VLSIDAn Efficient Method for Clock Skew Scheduling to Reduce Peak Current.Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu
2015DATEA novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics.Arunkumar Vijayakumar, Sandip Kundu
2015ICCDOnline mechanism for reliability and power-efficiency management of a dynamically reconfigurable core.Sudarshan Srinivasan, Israel Koren, Sandip Kundu
2014IOLTSOnline error detection and recovery in dataflow execution.Tiago A. O. Alves, Sandip Kundu, Leandro A. J. Marzulo, Felipe Maia Galvo Frana
2014VLSIDOn Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions.Raghavan Kumar, Siva Nishok Dhanuskodi, Sandip Kundu
2014VLSIDPerformance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core.Rance Rodrigues, Israel Koren, Sandip Kundu
2013ICCDOn dynamic polymorphing of a superscalar core for improving energy efficiency.Sudarshan Srinivasan, Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu
2013ICCDManaging test coverage uncertainty due to thermal noise in nano-CMOS: A case-study on an SRAM array.Vikram B. Suresh, Sandip Kundu
2013VLSIDImpact of Clock-Gating on Power Distribution Network Using Wavelet Analysis.Vinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu
2012SBAC-PADScalable Thread Scheduling in Asymmetric Multicores for Power Efficiency.Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu
2011DATEOn testing prebond dies with incomplete clock networks in a 3D IC using DLLs.Michael Buttrick, Sandip Kundu
2011DATEModeling manufacturing process variation for design and test.Sandip Kundu, Aswin Sreedhar
2011DATEOn design of test structures for lithographic process corner identification.Aswin Sreedhar, Sandip Kundu
2011DATEPhysically unclonable functions for embeded security based on lithographic variation.Aswin Sreedhar, Sandip Kundu
2011ICCDTask model for on-chip communication infrastructure design for multicore systems.Bharath Phanibhushana, Kunal P. Ganeshpure, Sandip Kundu
2011IOLTSOn graceful degradation of microprocessors in presence of faults via resource banking.Rance Rodrigues, Sandip Kundu
2011IOLTSOn graceful degradation of chip multiprocessors in presence of faults via flexible pooling of critical execution units.Rance Rodrigues, Sandip Kundu
2011ITCLithography aware critical area estimation and yield analysis.Priyamvada Vijayakumar, Vikram B. Suresh, Sandip Kundu
2010ICCDA study on performance benefits of core morphing in an asymmetric multicore processor.Anup Das, Rance Rodrigues, Israel Koren, Sandip Kundu
2010ITCModeling the impact of process variation on resistive bridge defects.S. Saqib Khursheed, Shida Zhong, Robert C. Aitken, Bashir M. Al-Hashimi, Sandip Kundu
2010ITCShadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor.Rance Rodrigues, Sandip Kundu, Omer Khan
2010VLSIDOptical Lithography Simulation with Focus Variation using Wavelet Transform.Rance Rodrigues, Sandip Kundu
2009DATEA self-adaptive system architecture to address transistor aging.Omer Khan, Sandip Kundu
2009DATEHardware/software co-design architecture for thermal management of chip multiprocessors.Omer Khan, Sandip Kundu
2009DATEA study on placement of post silicon clock tuning buffers for mitigating impact of process variation.Kelageri Nagaraj, Sandip Kundu
2009DATEImproving yield and reliability of chip multiprocessors.Abhisek Pan, Omer Khan, Sandip Kundu
2009DATEOn linewidth-based yield analysis for nanometer lithography.Aswin Sreedhar, Sandip Kundu
2009ICCDOptical lithography simulation using wavelet transform.Rance Rodrigues, Aswin Sreedhar, Sandip Kundu
2009ICCDStatistical timing analysis based on simulation of lithographic process.Aswin Sreedhar, Sandip Kundu
2009VLSIDAn ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays.Kunal P. Ganeshpure, Sandip Kundu
2008DATEOn Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits.Aswin Sreedhar, Alodeep Sanyal, Sandip Kundu
2008DDECSThe Guiding Light for Chip Testing.Sandip Kundu
2008ICCADA framework for predictive dynamic temperature management of microprocessor systems.Omer Khan, Sandip Kundu
2008ICCDModeling and analysis of non-rectangular transistors caused by lithographic distortions.Aswin Sreedhar, Sandip Kundu
2008IOLTSA Built-In Self-Test Scheme for Soft Error Rate Characterization.Alodeep Sanyal, Syed M. Alam, Sandip Kundu
2008ITCAn Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester Measurements.Kelageri Nagaraj, Sandip Kundu
2008ITCStatistical Yield Modeling for Sub-wavelength Lithography.Aswin Sreedhar, Sandip Kundu
2008VLSIDOn Common-Mode Skewed-Load and Broadside Tests.Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2007DACOn Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method.Ashesh Rastogi, Wei Chen, Sandip Kundu
2007DATEInteractive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults.Kunal P. Ganeshpure, Sandip Kundu
2007ICCDOn modeling impact of sub-wavelength lithography on transistors.Aswin Sreedhar, Sandip Kundu
2007IOLTSAccelerating Soft Error Rate Testing Through Pattern Selection.Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu
2007IOLTSOn Derating Soft Error Probability Based on Strength Filtering.Alodeep Sanyal, Sandip Kundu
2007ISCASA Study on Impact of Leakage Current on Dynamic Power.Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu
2007ITCOn ATPG for multiple aggressor crosstalk faults in presence of gate delays.Kunal P. Ganeshpure, Sandip Kundu
2007VLSIDAn Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect.Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu
2006DATEA design for failure analysis (DFFA) technique to ensure incorruptible signatures.Sandip Kundu
2006ICCDA Pattern Generation Technique for Maximizing Power Supply Currents.Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu
2006ICCDPower Droop Testing.Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
2006IOLTSAn Improved Technique for Reducing False Alarms Due to Soft Errors.Sandip Kundu, Ilia Polian
2006VLSIDTest Pattern Generation for Power Supply Droop Faults.Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu
2005ETSPath-oriented transition fault test generation considering operating conditions.Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2005ITCTransient fault characterization in dynamic noisy environments.Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker
2005VTSResistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.Ilia Polian, Sandip Kundu, Jean-Marc Gallire, Piet Engelke, Michel Renovell, Bernd Becker
2004DATEA Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit.Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang
2004ICCADStatic statistical timing analysis for latch-based pipeline designs.Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu
2004ITCTrends in manufacturing test methods and their implications.Sandip Kundu, T. M. Mak, Rajesh Galivanche
2003DATECircuit and Platform Design Challenges in Technologies beyond 90nm.Bill Grundmann, Rajesh Galivanche, Sandip Kundu
2003DATEOn the Characterization of Hard-to-Detect Bridging Faults.Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2003DATEOn Modeling Cross-Talk Faults.Sujit T. Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti
2003ETSOn path selection for delay fault testing considering operating conditions [logic IC testing].Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2003ITCOn-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding.Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2002DACOn output response compression in the presence of unknown output values.Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy
2001DACFast Statistical Timing Analysis By Probabilistic Event Propagation.Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic
2001VLSIDOn Fault-Simulation Through Embedded Memories On Large Industrial Designs.Sitaram Yadavalli, Sandip Kundu
2000ASPDACPerformance sensitivity analysis using statistical method and its applications to delay.Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu
2000ETSTest challenges in nanometer technologies.Sandip Kundu, Sanjay Sengupta, Rajesh Galivanche
1999ICCDOn Detecting Bridges Causing Timing Failures.Sreenivas Mandava, Sreejit Chakravarty, Sandip Kundu
1998ASPDACTiming Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial).Anirudh Devgan, Sandip Kundu
1998ITCGateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification.Sandip Kundu
1997DATEInductance analysis of on-chip interconnects [deep submicron CMOS].Sandip Kundu, Uttam Ghoshal
1997ICCADTiming analysis and optimization: from devices to systems (tutorial).Anirudh Devgan, Leon Stok, Sandip Kundu
1994DACMicroprocessor Testing: Which Technique is Best? (Panel).Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther
1994ICCADIncremental synthesis.Daniel Brand, Anthony D. Drumm, Sandip Kundu, Prakash Narain
1994ICCDMultifault Testable Circuits Based on Binary Parity Diagrams.Sandip Kundu
1993ITCDesign of Scan-Based Path-Delay-Testable Sequential Circuits.Ankan K. Pramanick, Sandip Kundu
1993VTSOn diagnosis of faults in a scan-chain.Sandip Kundu
1993VTSTestability preserving Boolean transforms for logic synthesis.Sandip Kundu, Ankan K. Pramanick
1992ITCA Small Test Generator for Large Designs.Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy
1989ICCDDesign of TSC checkers for implementation in CMOS technology.Sandip Kundu, Sudhakar M. Reddy
1988ICCADOn the design of robust multiple fault testable CMOS combinational logic circuits.Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha
1988ITCRobust Tests for Parity Trees.Sandip Kundu, Sudhakar M. Reddy