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Andreas Dandalis

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

9

Venues

4

Active years

1997–2001

Best venue rank

B

Where they publish

Papers

9 indexed papers, newest first.

YearVenueTitleAuthors
2001FPGAConfiguration compression for FPGA-based embedded systems.Andreas Dandalis, Viktor K. Prasanna
2001FPLRun-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers.Andreas Dandalis, Viktor K. Prasanna, Bharani Thiruvengadam
2000CHESA Comparative Study of Performance of AES Final Candidates Using FPGAs.Andreas Dandalis, Viktor K. Prasanna, Jos D. P. Rolim
2000FCCMAn Adaptive Cryptographic Engine for IPSec Architectures.Andreas Dandalis, Viktor K. Prasanna, Jos D. P. Rolim
2000FPLA Parallel Pipelined SAT Solver for FPGAs.Mark Redekopp, Andreas Dandalis
2000FPLEfficient Self-Reconfigurable Implementations Using On-chip Memory.Sameer Wadhwa, Andreas Dandalis
1998FCCMMapping Homogeneous Computations onto Dynamically Configurable Coarse-Grained Architectures.Andreas Dandalis, Viktor K. Prasanna
1998FPLSpace-efficient Mapping of 2D-DCT onto Dynamically Configurable Coarse-Grained Architectures.Andreas Dandalis, Viktor K. Prasanna
1997FPLFast parallel implementation of DFT using configurable devices.Andreas Dandalis, Viktor K. Prasanna