Andrs D. Garca
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
1999–2000
Best venue rank
A
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2000 | FPGA | Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. | Andrs D. Garca, Jean-Luc Danger, Wayne P. Burleson |
| 2000 | ISCAS | Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. | Andrs D. Garca, Wayne P. Burleson, Jean-Luc Danger |
| 1999 | FPL | Power Modelling in Field Programmable Gate Arrays (FPGA). | Andrs D. Garca, Wayne P. Burleson, Jean-Luc Danger |