| 2016 | VTS | Keynote address: Challenges and opportunities in electrical characterization and test for 14nm and below. | Andrzej J. Strojwas, Jacob A. Abraham, Hong Hao, Max M. Shulaker |
| 2014 | ICCAD | Sub-20 nm design technology co-optimization for standard cell logic. | Kaushik Vaidyanathan, Lars Liebmann, Andrzej J. Strojwas, Larry T. Pileggi |
| 2013 | DAC | Automatic clustering of wafer spatial signatures. | Wangyang Zhang, Xin Li, Sharad Saxena, Andrzej J. Strojwas, Rob A. Rutenbar |
| 2011 | DDECS | Cost effective scaling to 22nm and below technology nodes. | Andrzej J. Strojwas |
| 2010 | DAC | Who solves the variability problem? | Nagaraj Ns, Juan C. Rey, Jamil Kawa, Robert C. Aitken, Christian Ltkemeyer, Vijay Pitchumani, Andrzej J. Strojwas, Steve Trimberger |
| 2009 | DAC | Creating an affordable 22nm node using design-lithography co-optimization. | Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi |
| 2007 | DATE | DFM/DFY: should you trust the surgeon or the family doctor? | Marco Casale-Rossi, Andrzej J. Strojwas, Robert C. Aitken, Antun Domic, Carlo Guardiani, Philippe Magarshack, Douglas Pattullo, Joseph Sawicki |
| 2005 | DAC | Design methodology for IC manufacturability based on regular logic-bricks. | V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi |
| 2005 | DAC | Correlation-aware statistical timing analysis with non-gaussian delay distributions. | Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma |
| 2005 | ICCAD | Projection-based performance modeling for inter/intra-die variations. | Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J. Strojwas |
| 2005 | ICCAD | Statistical critical path analysis considering correlations. | Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark |
| 2004 | DAC | Routing architecture exploration for regular fabrics. | V. Kheterpal, Andrzej J. Strojwas, Lawrence T. Pileggi |
| 2003 | DAC | Exploring regular fabrics to optimize the performance-cost trade-off. | Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, Vyacheslav Rovner, Kim Yaw Tong |
| 2002 | DATE | Congestion-Aware Logic Synthesis. | Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas |
| 2000 | ASPDAC | Design for manufacturability: a path from system level to high yielding chips: embedded tutorial. | Andrzej J. Strojwas |
| 2000 | DAC | Impact of interconnect variations on the clock skew of a gigahertz microprocessor. | Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas |
| 2000 | DAC | When bad things happen to good chips (panel session). | N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang |
| 2000 | ICCAD | Design-Manufacturing Interface for 0.13 Micron and Below. | Andrzej J. Strojwas |
| 1999 | DAC | Model Order-Reduction of RC(L) Interconnect Including Variational Analysis. | Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas |
| 1999 | VLSID | A New Methodology for Concurrent Technology Development and Cell Library Optimization. | Marko P. Chew, Sharad Saxena, Thomas F. Cobourn, Purnendu K. Mozumder, Andrzej J. Strojwas |
| 1998 | DAC | Untitled record | Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas |
| 1997 | ICCAD | Timing analysis based on primitive path delay fault identification. | Mukund Sivaraman, Andrzej J. Strojwas |
| 1997 | VLSID | Primitive Path Delay Fault Identification. | Mukund Sivaraman, Andrzej J. Strojwas |
| 1996 | ICCAD | Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults. | Mukund Sivaraman, Andrzej J. Strojwas |
| 1996 | ISLPED | Manufacturability of low power CMOS technology solutions. | Andrzej J. Strojwas, Michele Quarantelli, J. Borel, Carlo Guardiani, Germano Nicollini, G. Crisenza, Bruno Franzini, J. Wiart |
| 1996 | VLSID | Diagnosis of parametric path delay faults. | Mukund Sivaraman, Andrzej J. Strojwas |
| 1996 | VTS | A diagnosability metric for parametric path delay faults. | Mukund Sivaraman, Andrzej J. Strojwas |
| 1995 | ITC | Test Vector Generation for Parametric Path Delay Faults. | Mukund Sivaraman, Andrzej J. Strojwas |
| 1994 | DAC | MONSTR: A Complete Thermal Simulator of Electronic Systems. | Vladimir A. Koval, Igor W. Farmaga, Andrzej J. Strojwas, Stephen W. Director |
| 1994 | ISCAS | Stochastic Interpolation Model Scheme for Statistical Circuit Design. | Jin-Qin Lu, Kimihiro Ogawa, Takehiko Adachi, Andrzej J. Strojwas |
| 1992 | ICCAD | A methodology for improved circuit simulation efficiency via topology-based variable accuracy device modeling. | Kimon W. Michaels, Andrzej J. Strojwas |
| 1991 | DAC | The Role of Timing Verification in Layout Synthesis. | Jacques Benkoski, Andrzej J. Strojwas |
| 1991 | DAC | Utilizing Logic Information in Multi-Level Timing Simulation. | Marko P. Chew, Andrzej J. Strojwas |
| 1991 | DAC | A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator. | D. M. H. Walker, Chris S. Kellen, Andrzej J. Strojwas |
| 1989 | DAC | Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator. | Jacques Benkoski, Andrzej J. Strojwas |
| 1989 | DAC | Design for Manufacturability and Yield. | Andrzej J. Strojwas |
| 1989 | ITC | Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator. | Jacques Benkoski, Andrzej J. Strojwas |
| 1986 | DAC | Yield of VLSI circuits: myths vs. reality (panel). | Andrzej J. Strojwas, Clark Beck, Dennis Buss, Tlin Erdim Mangir, Charles H. Stapper |
| 1985 | DAC | CMU-CAM system. | Andrzej J. Strojwas |