| 2025 | AAAI | InteDisUX: Intepretation-Guided Discriminative User-Centric Explanation for Time Series. | Viet-Hung Tran, Zichi Zhang, Tuan Dung Pham, Ngoc Phu Doan, Anh-Tuan Hoang, Peixin Li, Hans Vandierendonck, Ira Assent, Son T. Mai |
| 2025 | AAAI | WaveletMixer: A Multi-Resolution Wavelets Based MLP-Mixer for Multivariate Long-Term Time Series Forecasting. | Zichi Zhang, Tuan Dung Pham, Yimeng An, Ngoc Phu Doan, Majed Alsharari, Viet-Hung Tran, Anh-Tuan Hoang, Hans Vandierendonck, Son T. Mai |
| 2025 | DAC | DeepPUFSCA: Deep learning for Physical Unclonable Function attack based on Side Channel Analysis support. | Ngoc Phu Doan, Tuan Dung Pham, Zichi Zhang, Viet-Hung Tran, Jack Miskelly, Hans Vandierendonck, Anh-Tuan Hoang, Mire O'Neill, Son T. Mai |
| 2025 | SECRYPT | An Enhanced Two-Step CPA Side-Channel Analysis Attack on ML-KEM. | Mark Kennaway, Anh-Tuan Hoang, Ayesha Khalid, Ciara Rafferty, Mire O'Neill |
| 2022 | SECRYPT | Stacked Ensemble Model for Enhancing the DL based SCA. | Anh-Tuan Hoang, Neil Hanley, Ayesha Khalid, Dur-e-Shahwar Kundi, Mire O'Neill |
| 2014 | ISCAS | Pipeline scanning architecture with computation reduction for rectangle pattern matching in real-time traffic sign detection. | Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto, Mutsumi Omori |
| 2014 | ISCAS | FPGA implementation of feature extraction for colorectal endoscopic images with NBI magnification. | Tsubasa Mishima, Satoshi Shigemi, Anh-Tuan Hoang, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Rie Miyaki, Taiji Matsuo, Shigeto Yoshida, Shinji Tanaka |
| 2014 | ISCAS | Compact hardware oriented number recognition algorithm for real-time speed traffic-sign recognition. | Masaharu Yamamoto, Anh-Tuan Hoang, Mutsumi Omori, Tetsushi Koide |
| 2013 | FPGA | Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only). | Anh-Tuan Hoang, Takeshi Fujino |
| 2012 | DSD | Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit. | Hiroki Ito, Mitsuru Shiozaki, Anh-Tuan Hoang, Takeshi Fujino |
| 2012 | FPGA | Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA. | Anh-Tuan Hoang, Takeshi Fujino |