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Ashok K. Murugavel

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

8

Venues

4

Active years

2001–2004

Best venue rank

A*

Where they publish

Papers

8 indexed papers, newest first.

YearVenueTitleAuthors
2004VLSIDGate Sizing and Buffer Insertion using Economic Models for Power Optimization.Ashok K. Murugavel, N. Ranganathan
2004VLSIDGame Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis.Ashok K. Murugavel, N. Ranganathan
2003ICCDA Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization.N. Ranganathan, Ashok K. Murugavel
2003VLSIDA Game-Theoretic Approach for Binding in Behavioral Synthesis.Ashok K. Murugavel, N. Ranganathan
2002DACPetri net modeling of gate and interconnect delays for power estimation.Ashok K. Murugavel, N. Ranganathan
2002ISLPEDPower estimation of sequential circuits using hierarchical colored hardware petri net modeling.Ashok K. Murugavel, N. Ranganathan
2002VLSIDA Real Delay Switching Activity Simulator Based on Petri Net Modeling.Ashok K. Murugavel, N. Ranganathan
2001VLSIDAverage Power in Digital CMOS Circuits using Least Square Estimation.Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali