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Aviral Shrivastava

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

79

Venues

19

Active years

2000–2026

Best venue rank

A*

Where they publish

Papers

79 indexed papers, newest first.

YearVenueTitleAuthors
2026DATEPREFACE: Proactive Re-executions for Fault-aware Mixed-criticality Environments.Hwisoo So, Byeonggil Jun, Chanhee Lee, Hokeun Kim, Aviral Shrivastava
2025VLSIDTIPAngle: Traffic Tracking at City Scale by Pose Estimation of Pan and Tilt Intersection Cameras.Shreehari Jagadeesha, Edward Andert, Aviral Shrivastava
2024CASESPrimer on Data in Quantum Machine Learning.Aviral Shrivastava, Vinayak Sharma
2024DACConclave - Secure and Robust Cooperative Perception for Connected Autonomous Vehicle Using Authenticated Consensus and Trust Scoring.Edward Andert, Francis Mendoza, Hans Walter Behrens, Aviral Shrivastava
2024DACMaintaining Sanity: Algorithm-based Comprehensive Fault Tolerance for CNNs.Jinhyo Jung, Hwisoo So, Woobin Ko, Sumedh Shridhar Joshi, Yebon Kim, Yohan Ko, Aviral Shrivastava, Kyoungwoo Lee
2023ASPLOSExplainable-DSE: An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis.Shail Dave, Tony Nowatzki, Aviral Shrivastava
2023DATELearning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level.Behnaz Ranjbar, Florian Klemme, Paul R. Genssler, Hussam Amrouch, Jinhyo Jung, Shail Dave, Hwisoo So, Kyongwoo Lee, Aviral Shrivastava, Ji-Yung Lin, Pieter Weckx, Subrat Mishra, Francky Catthoor, Dwaipayan Biswas, Akash Kumar
2022DATEPathSeeker: A Fast Mapping Algorithm for CGRAs.Mahesh Balasubramanian, Aviral Shrivastava
2022DATECompatibility Checking for Autonomous Lane-Changing Assistance Systems.Po-Yu Huang, Kai-Wei Liu, Zong-Lun Li, Sanggu Park, Edward Andert, Chung-Wei Lin, Aviral Shrivastava
2022VTSSpecial Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems.Shail Dave, Alberto Marchisio, Muhammad Abdullah Hanif, Amira Guesmi, Aviral Shrivastava, Ihsen Alouani, Muhammad Shafique
2021DATECHITIN: A Comprehensive In-thread Instruction Replication Technique Against Transient Faults.Hwisoo So, Moslem Didehban, Jinhyo Jung, Aviral Shrivastava, Kyoungwoo Lee
2021ICCDComprehensive Failure Analysis against Soft Errors from Hardware and Software Perspectives.Yohan Ko, Hwisoo So, Jinhyo Jung, Kyoungwoo Lee, Aviral Shrivastava
2020ICASSPdMazeRunner: Optimizing Convolutions on Dataflow Accelerators.Shail Dave, Aviral Shrivastava, Youngbin Kim, Sasikanth Avancha, Kyoungwoo Lee
2019DACSoftware Approaches for In-time Resilience.Aviral Shrivastava, Moslem Didehban
2019DATEA Dependable Detection Mechanism for Intersection Management of Connected Autonomous Vehicles (Interactive Presentation).Rachel Dedinsky, Mohammad Khayatian, Mohammadreza Mehrabian, Aviral Shrivastava
2019DATEA software-level Redundant MultiThreading for Soft/Hard Error Detection and Recovery.Hwisoo So, Moslem Didehban, Aviral Shrivastava, Kyoungwoo Lee
2019ICCDStatic Function Prefetching for Efficient Code Management on Scratchpad Memory.Youngbin Kim, Kyoungwoo Lee, Aviral Shrivastava
2019MEMOCODEEncoding and monitoring responsibility sensitive safety rules for automated vehicles in signal temporal logic.Mohammad Hekmatnejad, Shakiba Yaghoubi, Adel Dokhanchi, Heni Ben Amor, Aviral Shrivastava, Lina J. Karam, Georgios Fainekos
2019VLSIDWCET-Aware Stack Frame Management of Embedded Systems Using Scratchpad Memories.Yooseong Kim, Mohammad Khayatian, Aviral Shrivastava
2019VLSIDEfficient Heap Data Management on Software Managed Manycore Architectures.Jinn-Pean Lin, Jing Lu, Jian Cai, Aviral Shrivastava
2018DACRAMP: resource-aware mapping for CGRAs.Shail Dave, Mahesh Balasubramanian, Aviral Shrivastava
2018DACAn efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems.Mohammadreza Mehrabian, Mohammad Khayatian, Ahmed Mousa, Aviral Shrivastava, Ya-Shian Li-Baboud, Patricia Derler, Edward R. Griffor, Hugo A. Andrade, Marc Weiss, John C. Eidson, Dhananjay M. Anand
2018DATELASER: A hardware/software approach to accelerate complicated loops on CGRAs.Mahesh Balasubramanian, Shail Dave, Aviral Shrivastava, Reiley Jeyapaul
2018DATEURECA: Unified register file for CGRAs.Shail Dave, Mahesh Balasubramanian, Aviral Shrivastava
2018DATEEXPERT: Effective and flexible error protection by redundant multithreading.Hwisoo So, Moslem Didehban, Yohan Ko, Aviral Shrivastava, Kyoungwoo Lee
2018RTSSRIM: Robust Intersection Management for Connected Autonomous Vehicles.Mohammad Khayatian, Mohammadreza Mehrabian, Aviral Shrivastava
2017DACCrossroads: Time-Sensitive Autonomous Intersection Management Technique.Edward Andert, Mohammad Khayatian, Aviral Shrivastava
2017DACInCheck: An In-application Recovery Scheme for Soft Errors.Moslem Didehban, Sai Ram Dheeraj Lokam, Aviral Shrivastava
2017DACA Testbed to Verify the Timing Behavior of Cyber-Physical Systems: Invited.Aviral Shrivastava, Mohammadreza Mehrabian, Mohammad Khayatian, Patricia Derler, Hugo A. Andrade, Kevin B. Stanton, Ya-Shian Li-Baboud, Edward R. Griffor, Marc Weiss, John C. Eidson
2017DATEReducing code management overhead in software-managed multicores.Jian Cai, Yooseong Kim, Youngbin Kim, Aviral Shrivastava, Kyoungwoo Lee
2017ICCADNEMESIS: A software approach for computing in presence of soft errors.Moslem Didehban, Aviral Shrivastava, Sai Ram Dheeraj Lokam
2016DACnZDC: a compiler technique for near zero silent data corruption.Moslem Didehban, Aviral Shrivastava
2016ICCADSplitting functions in code management on scratchpad memories.Youngbin Kim, Jian Cai, Yooseong Kim, Kyoungwoo Lee, Aviral Shrivastava
2016INFOCOMUrbanEye: An outdoor localization system for public transport.Rohit Verma, Aviral Shrivastava, Bivas Mitra, Sujoy Saha, Niloy Ganguly, Subrata Nandi, Sandip Chakraborty
2016MobisysMargdarshak: A Mobile Data Analytics based Commute Time Estimator cum Route Recommender.Rohit Verma, Aviral Shrivastava, Sandip Chakraborty, Bivas Mitra
2016VLSIDSoftware Coherence Management on Non-coherent Cache Multi-cores.Jian Cai, Aviral Shrivastava
2015CASESOptimization of multi-channel BCH error decoding for common cases.Russ Dill, Aviral Shrivastava, Hyunok Oh
2015DACGuidelines to design parity protected write-back L1 data cache.Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee, Aviral Shrivastava
2015DATEPath selection based acceleration of conditionals in CGRAs.ShriHari RajendranRadhika, Aviral Shrivastava, Mahdi Hamzeh
2015DATEEnabling multi-threaded applications on hybrid shared memory manycore architectures.Tushar Rawat, Aviral Shrivastava
2015RTASA predictable and command-level priority-based DRAM controller for mixed-criticality systems.Hokeun Kim, David Broman, Edward A. Lee, Michael Zimmer, Aviral Shrivastava, Junkwang Oh
2014CASESConstruction of GCCFG for inter-procedural optimizations in Software Managed Manycore (SMM) architectures.Bryce Holton, Ke Bai, Aviral Shrivastava, Harini Ramaprasad
2014DACBranch-Aware Loop Mapping on CGRAs.Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula
2014DACQuantitative Analysis of Control Flow Checking Mechanisms for Soft Errors.Aviral Shrivastava, Abhishek Rhisheekesan, Reiley Jeyapaul, Carole-Jean Wu
2014RTASWCET-aware dynamic code management on scratchpads for Software-Managed Multicores.Yooseong Kim, David Broman, Jian Cai, Aviral Shrivastava
2013DACREGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs).Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula
2013DACSSDM: smart stack data management for software managed multicores (SMMs).Jing Lu, Ke Bai, Aviral Shrivastava
2013DATEAutomatic and efficient heap data management for limited local memory multicore architectures.Ke Bai, Aviral Shrivastava
2012DACEPIMap: using epimorphism to map applications on CGRAs.Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula
2011CASESVector class on limited local memory (LLM) multi-core processors.Ke Bai, Di Lu, Aviral Shrivastava
2011CASESSmart cache cleaning: energy efficient vulnerability reduction in embedded processors.Reiley Jeyapaul, Aviral Shrivastava
2011DACCuMAPz: a tool to analyze memory access patterns in CUDA.Yooseong Kim, Aviral Shrivastava
2011ICPPUnSync: A Soft Error Resilient Redundant Multicore Architecture.Reiley Jeyapaul, Fei Hong, Abhishek Rhisheekesan, Aviral Shrivastava, Kyoungwoo Lee
2011ICPPEnabling Multithreading on CGRAs.Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula
2011ISLPEDFast and energy-efficient constant-coefficient FIR filters using residue number system.Piotr Patronik, Krzysztof S. Berezowski, Stanislaw J. Piestrak, Janusz Biernat, Aviral Shrivastava
2011VLSIDLA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches.Aarul Jain, Aviral Shrivastava, Chaitali Chakrabarti
2010DATEPower-accuracy tradeoffs in human activity transition detection.Jeffrey Boyd, Hari Sundaram, Aviral Shrivastava
2010SCOPESB2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems.Reiley Jeyapaul, Aviral Shrivastava
2009ASPDACA software solution for dynamic stack management on scratch pad memory.Arun Kannan, Aviral Shrivastava, Amit Pabalkar, Jongeun Lee
2009ASPDACCompiler-managed register file protection for energy-efficient soft error reduction.Jongeun Lee, Aviral Shrivastava
2009CASESExploiting residue number system for power-efficient digital signal processing in embedded processors.Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak
2009DATEStatic analysis to mitigate soft errors in register files.Jongeun Lee, Aviral Shrivastava
2009DATEFSAF: File system aware flash translation layer for NAND Flash Memories.Sai Krishna Mylavarapu, Siddharth Choudhuri, Aviral Shrivastava, Jongeun Lee, Tony Givargis
2009VLSIDCode Transformations for TLB Power Reduction.Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivastava
2008ASPDACA Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures.Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt
2008ASPDACSPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures.Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, Yunheung Paek
2008DATEHiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors.Sanghyun Park, Aviral Shrivastava, Yunheung Paek
2008HiPCSDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories.Amit Pabalkar, Aviral Shrivastava, Arun Kannan, Jongeun Lee
2008VLSIDPTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors.Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi
2008VLSIDPower Reduction of Functional Units Considering Temperature and Process Variations.Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2008VLSIDTemperature and Process Variations Aware Power Gating of Functional Units.Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2007DATEInteractive presentation: Functional and timing validation of partially bypassed processor pipelines.Qiang Zhu, Aviral Shrivastava, Nikil D. Dutt
2006CASESMitigating soft error failures for multimedia applications by selective data protection.Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt, Nalini Venkatasubramanian
2006DATEAutomatic generation of operation tables for fast exploration of bypasses in embedded processors.Sanghyun Park, Eugene Earlie, Aviral Shrivastava, Alex Nicolau, Nikil D. Dutt, Yunheung Paek
2005CASESCompilation techniques for energy reduction in horizontally partitioned cache architectures.Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt
2005DATEPBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors.Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Eugene Earlie
2004ASPDACEnergy efficient code generation exploiting reduced bit-width instruction set architectures (rISA).Aviral Shrivastava, Nikil D. Dutt
2002DATEAn Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs.Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau
2000VLSIDOptimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming.Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar, M. Balakrishnan