Carles Hernndez
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
55
Venues
18
Active years
2010–2025
Best venue rank
A*
Where they publish
Papers
55 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | SAFECOMP | Improving Out-of-Distribution Detection via Test-Time Augmentation. | Imanol Allende, Nicholas Mc Guire, Javier del Campo, Carles Hernndez |
| 2023 | DATE | NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips. | Xabier Iturbe, Nassim Abderrahmane, Jaume Abella, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Anglica Dvila, Arne Erdmann, Carles Estrada, Ander Fernndez, Anna Fontanelli, Jos Flich, Gianluca Furano, Alejandro Hernn Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernndez, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernab Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Lujn, Karel Masark, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov |
| 2023 | DATE | BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes. | Ilya Tuzov, David de Andrs, Juan-Carlos Ruiz-Garcia, Carles Hernndez |
| 2023 | ETS | A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors. | Jens Anders, Pablo Andreu, Bernd Becker, Steffen Becker, Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Nourhan Elhamawy, Tobias Faller, Carles Hernndez, Nele Mentens, Mahnaz Namazi Rizi, Ilia Polian, Abolfazl Sajadi, Matthias Sauer, Denis Schwachhofer, Matteo Sonza Reorda, Todor Stefanov, Ilya Tuzov, Stefan Wagner, Nusa Zidaric |
| 2022 | DATE | SafeSU-2: a Safe Statistics Unit for Space MPSoCs. | Guillem Cabo, Sergi Alcaide, Carles Hernndez, Pedro Benedicte, Francisco Bas, Fabio Mazzocchetti, Jaume Abella |
| 2022 | DATE | The SELENE Deep Learning Acceleration Framework for Safety-related Applications. | Laura Medina, Salva Carrion, Pablo Andreu, Toms Picornell, Jos Flich, Carles Hernndez, Michael Sandoval, Markel Sainz, Charles-Alexis Lefebvre, Martin Rnnbck, Martin Matschnig, Matthias Wess, Herbert Taucher |
| 2022 | ICIP | Efficient Inference Of Image-Based Neural Network Models In Reconfigurable Systems With Pruning And Quantization. | Jos Flich, Laura Medina, Izan Cataln, Carles Hernndez, Andrea Bragagnolo, Fabrice Auzanneau, David Briand |
| 2021 | DATE | From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience. | Jos Flich, Rafael Tornero, David Rodriguez, Davide Russo, Jos Maria Martnez, Carles Hernndez |
| 2021 | ETS | Security, Reliability and Test Aspects of the RISC-V Ecosystem. | Jaume Abella, Sergi Alcaide, Jens Anders, Francisco Bas, Steffen Becker, Elke De Mulder, Nourhan Elhamawy, Frank K. Grkaynak, Helena Handschuh, Carles Hernndez, Michael Hutter, Leonidas Kosmidis, Ilia Polian, Matthias Sauer, Stefan Wagner, Francesco Regazzoni |
| 2021 | ETS | SafeSU: an Extended Statistics Unit for Multicore Timing Interference. | Guillem Cabo, Francisco Bas, Ruben Lorenzo, David Trilla, Sergi Alcaide, Miquel Moret, Carles Hernndez, Jaume Abella |
| 2021 | FPL | HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem. | Vatistas Kostalabros, Jordi Ribes-Gonzlez, Oriol Farrs, Miquel Moret, Carles Hernndez |
| 2021 | ICCAD | Improving the Robustness of Redundant Execution with Register File Randomization. | Ilya Tuzov, Pablo Andreu, Laura Medina, Toms Picornell, Antonio Robles, Pedro Lpez, Jos Flich, Carles Hernndez |
| 2020 | DSD | SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems. | Carles Hernndez, Jos Flich, Roberto Paredes, Charles-Alexis Lefebvre, Imanol Allende, Jaume Abella, David Trillin, Martin Matschnig, Bernhard Fischer, Konrad Schwarz, Jan Kiszka, Martin Rnnbck, Johan Klockars, Nicholas Mc Guire, Franz Rammerstorfer, Christian Schwarzl, Franck Wartel, Dierk Ldemann, Mikel Labayen |
| 2020 | DSN | Workshop on High-performance Computing Platforms for Dependable Autonomous Systems. | Carles Hernndez, Jaume Abella, Mikel Azkarate-askasua, Roman Obermaisser |
| 2020 | DSN | Software-Only Triple Diverse Redundancy on GPUs for Autonomous Driving Platforms. | Sergi Alcaide Portet, Leonidas Kosmidis, Carles Hernndez, Jaume Abella |
| 2019 | ASPDAC | Towards limiting the impact of timing anomalies in complex real-time processors. | Pedro Benedicte, Jaume Abella, Carles Hernndez, Enrico Mezzetti, Francisco J. Cazorla |
| 2019 | DAC | DCFNoC: A Delayed Conflict-Free Time Division Multiplexing Network on Chip. | Toms Picornell, Jos Flich, Carles Hernndez, Jos Duato |
| 2019 | DATE | High-Integrity GPU Designs for Critical Real-Time Automotive Systems. | Sergi Alcaide, Leonidas Kosmidis, Carles Hernndez, Jaume Abella |
| 2019 | DATE | LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache. | Pedro Benedicte, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2019 | DATE | Maximum-Contention Control Unit (MCCU): Resource Access Count and Contention Time Enforcement. | Jordi Cardona, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2019 | DSD | Challenges in Deeply Heterogeneous High Performance Systems. | Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, Jos Flich, Carles Hernndez, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavil, Marina Zapater |
| 2019 | DSD | An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior. | David Trilla, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2019 | DSD | Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation. | David Trilla, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2019 | IOLTS | Software-only Diverse Redundancy on GPUs for Autonomous Driving Platforms. | Sergi Alcaide, Leonidas Kosmidis, Carles Hernndez, Jaume Abella |
| 2018 | DAC | Cache side-channel attacks and time-predictability in high-performance critical real-time systems. | David Trilla, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2018 | DATE | Design and integration of hierarchical-placement multi-level caches for real-time systems. | Pedro Benedicte, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2018 | ECRTS | HWP: Hardware Support to Reconcile Cache Energy, Complexity, Performance and WCET Estimates in Multicore Real-Time Systems. | Pedro Benedicte, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2018 | SAC | RPR: a random replacement policy with limited pathological replacements. | Pedro Benedicte, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2018 | RTSS | NoCo: ILP-Based Worst-Case Contention Estimation for Mesh Real-Time Manycores. | Jordi Cardona, Carles Hernndez, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla |
| 2017 | DAC | DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis. | Sergi Alcaide, Carles Hernndez, Antoni Roca, Jaume Abella |
| 2017 | DATE | Probabilistic timing analysis on time-randomized platforms for the space domain. | Mikel Fernndez, David Morales, Leonidas Kosmidis, Alen Bardizbanyan, Ian Broster, Carles Hernndez, Eduardo Quiones, Jaume Abella, Francisco J. Cazorla, Paulo Machado, Luca Fossati |
| 2017 | DATE | Design and implementation of a fair credit-based bandwidth sharing scheme for buses. | Mladen Slijepcevic, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2017 | DSD | Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis. | Mladen Slijepcevic, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2017 | ECRTS | Design and Implementation of a Time Predictable Processor: Evaluation With a Space Case Study. | Carles Hernndez, Jaume Abella, Francisco J. Cazorla, Alen Bardizbanyan, Jan Andersson, Fabrice Cros, Franck Wartel |
| 2017 | RTSS | Work-in-Progress Paper: An Analysis of the Impact of Dependencies on Probabilistic Timing Analysis and Task Scheduling. | Enrico Mezzetti, Jaume Abella, Carles Hernndez, Francisco J. Cazorla |
| 2016 | DAC | Random modulo: a new processor cache design for real-time critical systems. | Carles Hernndez, Jaume Abella, Andrea Gianarro, Jan Andersson, Francisco J. Cazorla |
| 2016 | DATE | Improving performance guarantees in wormhole mesh NoC designs. | Milos Panic, Carles Hernndez, Jaume Abella, Antoni Roca, Eduardo Quiones, Francisco J. Cazorla |
| 2016 | DSD | PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis. | Francisco J. Cazorla, Jaume Abella, Jan Andersson, Tullio Vardanega, Francis Vatrinet, Iain Bate, Ian Broster, Mikel Azkarate-askasua, Franck Wartel, Liliana Cucu, Fabrice Cros, Glenn Farrall, Adriana Gogonel, Andrea Gianarro, Benoit Triquet, Carles Hernndez, Code Lo, Cristian Maxim, David Morales, Eduardo Quiones, Enrico Mezzetti, Leonidas Kosmidis, Irune Agirre, Mikel Fernndez, Mladen Slijepcevic, Philippa Conmy, Walid Talaboulma |
| 2016 | DSD | pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems. | Mladen Slijepcevic, Mikel Fernndez, Carles Hernndez, Jaume Abella, Eduardo Quiones, Francisco J. Cazorla |
| 2016 | IOLTS | Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection. | Jaime Espinosa, Carles Hernndez, Jaume Abella |
| 2016 | IOLTS | Resilient random modulo cache memories for probabilistically-analyzable real-time systems. | David Trilla, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2016 | RTAS | Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems. | Milos Panic, Carles Hernndez, Eduardo Quiones, Jaume Abella, Francisco J. Cazorla |
| 2015 | DAC | Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification. | Jaime Espinosa, Carles Hernndez, Jaume Abella, David de Andrs, Juan-Carlos Ruiz-Garcia |
| 2015 | DATE | Low-cost checkpointing in automotive safety-relevant systems. | Carles Hernndez, Jaume Abella |
| 2015 | DSD | IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis. | Irune Agirre, Mikel Azkarate-askasua, Carles Hernndez, Jaume Abella, Jon Prez, Tullio Vardanega, Francisco J. Cazorla |
| 2015 | DSD | Enabling TDMA Arbitration in the Context of MBPTA. | Milos Panic, Jaume Abella, Carles Hernndez, Eduardo Quiones, Theo Ungerer, Francisco J. Cazorla |
| 2015 | DSD | CAP: Communication-Aware Allocation Algorithm for Real-Time Parallel Applications on Many-Cores. | Milos Panic, Eduardo Quiones, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2015 | IOLTS | Characterizing fault propagation in safety-critical processor designs. | Jaime Espinosa, Carles Hernndez, Jaume Abella |
| 2014 | DAC | LiVe: Timely Error Detection in Light-Lockstep Safety Critical Systems. | Carles Hernndez, Jaume Abella |
| 2014 | EMSOFT | Parallel many-core avionics systems. | Milos Panic, Eduardo Quiones, Pavel G. Zaykov, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2012 | EuroPar | Addressing Link Degradation in NoC-Based ULSI Designs. | Carles Hernndez, Federico Silla, Jos Duato |
| 2012 | ICPP | Enabling High-Performance Crossbars through a Floorplan-Aware Design. | Antoni Roca, Carles Hernndez, Jos Flich, Federico Silla, Jos Duato |
| 2011 | ICPP | Energy and Performance Efficient Thread Mapping in NoC-Based CMPs under Process Variations. | Carles Hernndez, Federico Silla, Jos Duato |
| 2011 | ICPP | A Distributed Switch Architecture for On-Chip Networks. | Antoni Roca, Carles Hernndez, Jos Flich, Federico Silla, Jos Duato |
| 2010 | DATE | A methodology for the characterization of process variation in NoC links. | Carles Hernndez, Federico Silla, Jos Duato |