| 2023 | ISCAS | Live Demonstration: A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy. | Jian-Lin Zeng, Tsung-Yi Wu, Don-Gey Liu, Ching-Hwa Cheng |
| 2023 | ISCAS | A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy. | Jian-Lin Zeng, Tsung-Yi Wu, Don-Gey Liu, Ching-Hwa Cheng |
| 2021 | ISCAS | The Performance-Complexity Efficient Time-to-Digit and Data-Processing Chips Design and Validation for a LiDAR System. | Ching-Hwa Cheng, Ching-Kun Chao, Kai-Chun Yeh, Don-Gey Liu, Sheng-Di Lin |
| 2021 | ISCAS | An Intelligent Image-Based Force Sensing System Development to Assist Robot-Arm Surgery. | Pham Minh Dung, Ching-Hwa Cheng, Don-Gey Liu |
| 2020 | ASPDAC | A Quantity Evaluation and Reconfiguration Mechanism for Signal- and Power-Interconnections in 3D-Stacking System. | Ching-Hwa Cheng |
| 2020 | ISCAS | Development of a Portable Self-Guidance Rescue Car and a 3D-Screen LIDAR Mapping System. | Ching-Hwa Cheng, Pham Minh Dung, Tang-Chieh Liu |
| 2020 | ISCAS | Design and Implementation of a Pre-Surgical Investigation System by VR+AR+MR Techniques. | Ching-Hwa Cheng, Huy Anh Nguyen, Tang-Chieh Liu |
| 2019 | DDECS | Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems. | Ching-Hwa Cheng, Tang-Chieh Liu |
| 2016 | ASPDAC | A variable-voltage low-power technique for digital circuit system. | An-Tai Xiao, Yung-Siang Miao, Ching-Hwa Cheng, Jiun-In Guo |
| 2015 | ISCAS | A wireless panoramic endoscope system design and implementation for minimally invasive surgery. | Ching-Hwa Cheng, Sheng-Ping Hung, Jiun-In Guo, Kai-Che Liu, Jungle Chi-Hsiang Wu |
| 2014 | ISCAS | A panoramic endoscope design and implementation for Minimally Invasive Surgery. | Chun-Hsiang Peng, Ching-Hwa Cheng |
| 2013 | ISCAS | A low-cost scalable Voltage-Frequency Adjustor for implementing low-power systems. | Ching-Hwa Cheng, Sheng-Wei Hsu, Jiun-In Guo |
| 2011 | ASPDAC | A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. | Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng |
| 2011 | ASPDAC | Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism. | Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo |
| 2011 | ASPDAC | A low-power management technique for high-performance domino circuits. | Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo |
| 2011 | DSN | Built-in fine resolution clipping with calibration technique for high-speed testing by using wireless testers. | Ching-Hwa Cheng, Chen-I Chung |
| 2011 | DSN | A digitalized management mechanism for low-cost low-power multiple-voltage 3D designs. | Ching-Hwa Cheng, Ming-Hsuan Wu, Pin-Jui Lai, Chia-Hao Ku |
| 2010 | ASPDAC | Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. | Chen-I Chung, Shuo-Wen Chang, Feng-Tso Chien, Ching-Hwa Cheng |
| 2010 | ASPDAC | Built-in self at-speed delay binning and calibration mechanism in wireless test platform. | Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng |
| 2010 | ASPDAC | Dynamic voltage domain assignment technique for low power performance manageable cell based design. | Elone Lee, Feng-Tso Chien, Ching-Hwa Cheng, Jiun-In Guo |
| 2009 | ASPDAC | A full-synthesizable high-precision built-in delay time measurement circuit. | Ming-Chien Tsai, Ching-Hwa Cheng |
| 2009 | ASPDAC | CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. | Chin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo |
| 2009 | ISCAS | A Multi-standard Video Decoder for High Definition Video Applications. | Cheng-An Chien, Chih-Da Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng |
| 2009 | ITC | Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. | Chen-I Chung, Shuo-Wen Chang, Ching-Hwa Cheng |
| 2008 | VTS | An All-Digital High-Precision Built-In Delay Time Measurement Circuit. | Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang |
| 2007 | ISCAS | Noise-Aware Floorplanning for Fast Power Supply Network Design. | Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yiwen Wang, Ching-Hwa Cheng |
| 2007 | VTS | Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit. | Hsiang-Hui Huang, Ching-Hwa Cheng |
| 2000 | ICCAD | Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. | Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang |
| 1995 | VLSID | An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors. | Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen |
| 1994 | EDCC | An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors. | Yung-Yuan Chen, Ching-Hwa Cheng, Yung-Ci Chou |