| 2019 | ISCAS | A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits. | Maryem Benyoussef, Claude Thibeault, Yvon Savaria |
| 2018 | VTS | Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits. | Omar Al-Terkawi Hasib, Daniel Crepeau, Thomas Awad, Andrei Dulipovici, Yvon Savaria, Claude Thibeault |
| 2017 | VTS | A new delay testing signal scheme robust to power distribution network impedance variation. | Claude Thibeault, Ali Louati |
| 2016 | ACSSC | A multi-Gbps unrolled hardware list decoder for a systematic polar code. | Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Mller, Andreas Peter Burg, Claude Thibeault, Warren J. Gross |
| 2016 | ICASSP | Partitioned successive-cancellation list decoding of polar codes. | Seyyed Ali Hashemi, Alexios Balatsoukas-Stimming, Pascal Giard, Claude Thibeault, Warren J. Gross |
| 2016 | ISCAS | A practical design method for prototyping self-timed processors using FPGAs. | Mickal Fiorentino, Yvon Savaria, Claude Thibeault, Pascal Gervais |
| 2016 | ISCAS | Hardware decoders for polar codes: An overview. | Pascal Giard, Gabi Sarkis, Alexios Balatsoukas-Stimming, YouZhe Fan, Chi-Ying Tsui, Andreas Peter Burg, Claude Thibeault, Warren J. Gross |
| 2016 | VTS | WeSPer: A flexible small delay defect quality metric. | Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault |
| 2015 | IOLTS | Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis. | Anis Souari, Claude Thibeault, Yves Blaquire, Raoul Velazco |
| 2015 | VTS | Foreword. | Claude Thibeault |
| 2014 | ICASSP | Fast software polar decoders. | Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross |
| 2014 | IOLTS | Multi-abstraction level signature generation and comparison based on radiation single event upset. | Christelle Hobeika, Simon Pichette, M. A. Leonard, Claude Thibeault, Jean-Franois Boland, Yves Audet |
| 2014 | MEMOCODE | Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications. | Khaza Anuarul Hoque, Otmane At Mohamed, Yvon Savaria, Claude Thibeault |
| 2013 | IWCMC | Multi-user Multi-Carrier Differential Chaos Shift Keying communication system. | Georges Kaddoum, Francois-Dominique Richardson, Sarra Adouni, Franois Gagnon, Claude Thibeault |
| 2012 | IECON | FPGA implementation and evaluation of discrete-time chaotic generators circuits. | Pascal Giard, Georges Kaddoum, Franois Gagnon, Claude Thibeault |
| 2007 | VTS | On a New Outlier Rejection Technique. | Claude Thibeault |
| 2004 | VTS | On New Current Signatures and Adaptive Test Technique Combination. | Claude Thibeault |
| 2002 | VTS | Speeding-Up IDDQ Measurements. | Claude Thibeault |
| 2001 | VTS | Tools for the Characterization of Bipolar CML Testability. | Ginette Mont, Bernard Antaki, Serge Patenaude, Yvon Savaria, Claude Thibeault, Pieter M. Trouborst |
| 2000 | ITC | Improving Delta-I_DDQ-based test methods. | Claude Thibeault |
| 2000 | VTS | Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm. | Claude Thibeault |
| 1999 | ITC | An histogram based procedure for current testing of active defects. | Claude Thibeault |
| 1999 | VTS | On the Comparison of IDDQ and IDDQ Testing. | Claude Thibeault |
| 1998 | ITC | Diagnosis method based on ΔIddq probabilistic signatures: experimental results. | Claude Thibeault, Luc Boisvert |
| 1997 | VTS | A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures. | Claude Thibeault |
| 1995 | VTS | Detection and location of faults and defects using digital signal processing. | Claude Thibeault |