| 2017 | FCCM | A Network-on-Chip Based H.264 Video Decoder Prototype Implemented on FPGAs. | Ian J. Barge, Cristinel Ababei |
| 2017 | FIE | Working on a start-up: A case for an applied entrepreneurship oriented course for senior undergraduates. | Cristinel Ababei |
| 2011 | CEC | A new fault-tolerant and congestion-aware adaptive routing algorithm for regular Networks-on-Chip. | Hamed Sajjadi Kia, Cristinel Ababei |
| 2010 | DAC | Network on chip design and optimization using specialized influence models. | Cristinel Ababei |
| 2009 | FPGA | Parallel placement for FPGAs revisited. | Cristinel Ababei |
| 2005 | ASPDAC | Three-dimensional place and route for FPGAs. | Cristinel Ababei, Hushrav Mogal, Kia Bazargan |
| 2005 | FPGA | 3D FPGAs: placement, routing, and architecture evaluation (abstract only). | Cristinel Ababei, Hushrav Mogal, Kia Bazargan |
| 2005 | FPGA | HARP: hard-wired routing pattern FPGAs. | Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh |
| 2004 | FPL | TPR: Three-D Place and Route for FPGAs. | Cristinel Ababei |
| 2004 | FPL | Exploring Potential Benefits of 3D FPGA Integration. | Cristinel Ababei, Pongstorn Maidee, Kia Bazargan |
| 2003 | DAC | Fast timing-driven partitioning-based placement for island style FPGAs. | Pongstorn Maidee, Cristinel Ababei, Kia Bazargan |
| 2003 | ICCAD | Placement Method Targeting Predictability Robustness and Performance. | Cristinel Ababei, Kia Bazargan |
| 2003 | VLSID | Timing Minimization by Statistical Timing hMetis-based Partitioning. | Cristinel Ababei, Kia Bazargan |
| 2002 | DATE | Statistical Timing Driven Partitioning for VLSI Circuits. | Cristinel Ababei, Kia Bazargan |
| 2002 | ICCAD | Multi-objective circuit partitioning for cutsize and path-based delay minimization. | Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis |
| 2000 | ISCAS | Improving simulation efficiency for circuit-level power estimation [CMOS]. | Radu Marculescu, Cristinel Ababei |