Skip to content

Daisuke Suzuki

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

25

Venues

15

Active years

2005–2026

Best venue rank

A*

Where they publish

Papers

25 indexed papers, newest first.

YearVenueTitleAuthors
2026HCIDriving Strategies of Railway Drivers Practicing Energy-Efficient Operation Considering Signal Aspects.Tamaki Ueda, Daisuke Suzuki, Kazuma Matsui, Chizuru Nakagawa, Tomoyuki Ogawa, Hiroyuki Sako, Yuta Yamamoto
2022ACNSTowards Isolated AI Accelerators with OP-TEE on SoC-FPGAs.Tsunato Nakai, Daisuke Suzuki, Takeshi Fujino
2022LRECConstruction of a Quality Estimation Dataset for Automatic Evaluation of Japanese Grammatical Error Correction.Daisuke Suzuki, Yujin Takahashi, Ikumi Yamashita, Taichi Aida, Tosho Hirasawa, Michitaka Nakatsuji, Masato Mita, Mamoru Komachi
2021ACNSTowards Trained Model Confidentiality and Integrity Using Trusted Execution Environments.Tsunato Nakai, Daisuke Suzuki, Takeshi Fujino
2021SAFECOMPEvaluation Framework for Performance Limitation of Autonomous Systems Under Sensor Attack.Koichi Shimizu, Daisuke Suzuki, Ryo Muramatsu, Hisashi Mori, Tomoyuki Nagatsuka, Tsutomu Matsumoto
2019CCSA Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar.Noriyuki Miura, Tatsuya Machida, Kohei Matsuda, Makoto Nagata, Shoei Nashimoto, Daisuke Suzuki
2018CCSSensor CON-Fusion: Defeating Kalman Filter in Signal Injection Attack.Shoei Nashimoto, Daisuke Suzuki, Takeshi Sugawara, Kazuo Sakiyama
2018FPGADesign of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only).Daisuke Suzuki, Takahiro Hanyu
2017DATEThree-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor.Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui
2016FPLA low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure.Daisuke Suzuki, Takahiro Hanyu
2016IECONZero-cross switching control of halogen lamp heater with delta-sigma modulator.Daisuke Suzuki, Akihiko Yoneya
2015DATESpintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm.Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki
2014CHESReversing Stealthy Dopant-Level Circuits.Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino
2013CHESOn Measurable Side-Channel Leaks Inside ASIC Design Primitives.Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
2013RO-MANCross-regional comparative study of dimensions of people's attitudes toward robots.Akihito Fujita, Daisuke Suzuki, Hiroyuki Umemuro
2012FDTCCircuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI.Takeshi Sugawara, Daisuke Suzuki, Toshihiro Katashita
2012HRIDimensions of people's attitudes toward robots.Daisuke Suzuki, Hiroyuki Umemuro
2010CHESThe Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes.Daisuke Suzuki, Koichi Shimizu
2009CHESA Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques.Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh
2009HCIA Study of Auditory Warning Signals for the Design Guidelines of Man-Machine Interfaces.Mie Nakatani, Daisuke Suzuki, Nobuchika Sakata, Shogo Nishida
2008CANSHigh-Speed Search System for PGP Passphrases.Koichi Shimizu, Daisuke Suzuki, Toyohiro Tsurumaru
2007CHESHow to Maximize the Potential of FPGA Resources for Modular Exponentiation.Daisuke Suzuki
2006ACLWord Vectors and Two Kinds of Similarity.Akira Utsumi, Daisuke Suzuki
2006CHESSecurity Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style.Daisuke Suzuki, Minoru Saeki
2005CHESDPA Leakage Models for CMOS Logic Circuits.Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa