| 2025 | SOFTCOM | A Power Consumption Model for Customer Premise Equipment: Methodology and Application. | Robin Dethienne, Jrme Louveaux, David Bol |
| 2024 | ISCAS | A Narrowband RF Front End in 22-nm FD-SOI Featuring a Programmable Low-Noise Amplifier with a Configurable Noise-Power Trade-Off. | Marco Gonzalez, Pol Maistriaux, David Bol |
| 2024 | PIMRC | A Parametric Power Model of Multi-Band Sub-6 GHz Cellular Base Stations Using On-Site Measurements. | Louis Golard, Youssef Agram, Franois Rottenberg, Franois Quitin, David Bol, Jrme Louveaux |
| 2023 | DATE | Post-Silicon Optimization of a Highly Programmable 64-MHz PLL Achieving 2.7-5.7 μW. | Marco Gonzalez, David Bol |
| 2021 | ACSSC | A Two-User Successive Interference Cancellation LoRa Receiver with Soft-Decoding. | Mathieu Xhonneux, Joachim Tapparel, Pter Scheepers, Orion Afisiadis, Alexios Balatsoukas-Stimming, David Bol, Jrme Louveaux, Andreas Burg |
| 2021 | DATE | Moore's Law and ICT Innovation in the Anthropocene. | David Bol, Thibault Pirson, Rmi Dekimpe |
| 2020 | ISCAS | A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas. | Charlotte Frenkel, Jean-Didier Legat, David Bol |
| 2019 | ISCAS | A 65-nm 738k-Synapse/mm | Charlotte Frenkel, Jean-Didier Legat, David Bol |
| 2019 | ISCAS | A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells. | Ludovic Moreau, Rmi Dekimpe, David Bol |
| 2018 | CCS | Demonstrating an LPPN Processor. | Dina Kamel, Davide Bellizia, Franois-Xavier Standaert, Denis Flandre, David Bol |
| 2018 | DATE | Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics. | Thomas Haine, Johan Segers, Denis Flandre, David Bol |
| 2017 | ISCAS | A fully-synthesized 20-gate digital spike-based synapse with embedded online learning. | Charlotte Frenkel, Giacomo Indiveri, Jean-Didier Legat, David Bol |
| 2017 | ISCAS | Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits. | Franois Stas, David Bol |
| 2017 | ISCAS | A 0.4V 0.08fJ/cycle retentive True-Single-Phase-Clock 18T Flip-Flop in 28nm FDSOI CMOS. | Franois Stas, David Bol |
| 2015 | ISCAS | Analysis and optimization for dynamic read stability in 28nm SRAM bitcells. | Ahmed T. Elthakeb, Thomas Haine, Denis Flandre, Yehea Ismail, Hamdy Abd Elhamid, David Bol |
| 2014 | ISCAS | Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes. | Franois Botman, Julien De Vos, Sebastien Bernard, Franois Stas, Jean-Didier Legat, David Bol |
| 2013 | ISLPED | Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology. | Guerric de Streel, David Bol |
| 2012 | CHES | Towards Green Cryptography: A Comparison of Lightweight Ciphers from the Energy Viewpoint. | Stphanie Kerckhof, Franois Durvaux, Cdric Hocquet, David Bol, Franois-Xavier Standaert |
| 2010 | ISCAS | Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits. | David Bol, Cdric Hocquet, Denis Flandre, Jean-Didier Legat |
| 2009 | ISLPED | Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits. | David Bol, Denis Flandre, Jean-Didier Legat |
| 2009 | ISLPED | Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic. | David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat |
| 2008 | ICCD | Analysis and minimization of practical energy in 45nm subthreshold logic circuits. | David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat |