| 2012 | DATE | Hazard driven test generation for SMT processors. | Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis |
| 1999 | ICCD | Evaluation of Computing in Memory Architectures for Digital Image Processing Applications. | David L. Landis, Paul T. Hulina, Scott Deno, Luke Roth, Lee D. Coraor |
| 1999 | RSP | A Rapid Prototyping Methodology for Reverse Engineering of Legacy Electronic Systems. | Scott Deno, David L. Landis, Paul T. Hulina, Sanjay Balasubramanian |
| 1999 | RSP | Language-Based Rapid Prototyping Methods for Legacy System Re-Engineering and Re-Use. | David L. Landis, Praveen Guddeti, Paul T. Hulina, Lee D. Coraor |
| 1996 | VTS | A novel built-in current sensor for I | Stephan P. Athan, David L. Landis, Sami A. Al-Arian |
| 1992 | ITC | Applications of the IEEE P1149.5 Module Test and Maintenance Bus. | David L. Landis, Chuck Hudson, Patrick F. McHugh |
| 1990 | ITC | Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration. | David L. Landis, Padmaraj Singh |
| 1989 | ICCD | Systolic L-U decomposition array with a new reciprocal cell. | Vijay K. Jain, David L. Landis, C. E. Alvarez |
| 1989 | ITC | A Self-Test System Architecture for Reconfigurable WSI. | David L. Landis |
| 1988 | ITC | Evaluation of System BIST Using Computational Performance Measures. | David L. Landis, Daniel C. Muha |
| 1987 | ICPP | Influence of Built-In Self Test on the Performance of Fault Tolerant VLSI Multiprocessors. | David L. Landis, Daniel C. Muha, William A. Check |