| 2024 | DAC | Beyond Inference: Performance Analysis of DNN Server Overheads for Computer Vision. | Ahmed F. AbouElhamayed, Susanne Balle, Deshanand P. Singh, Mohamed S. Abdelfattah |
| 2015 | FPGA | High-Level Design Tools for Floating Point FPGAs. | Deshanand P. Singh, Bogdan Pasca, Tomasz S. Czajkowski |
| 2013 | ASPDAC | Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platforms. | Doris Chen, Deshanand P. Singh |
| 2013 | FPGA | Harnessing the power of FPGAs using altera's OpenCL compiler. | Deshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling |
| 2012 | FPL | Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filtering. | Doris Chen, Deshanand P. Singh |
| 2012 | FPL | From opencl to high-performance hardware on FPGAS. | Tomasz S. Czajkowski, Utku Aydonat, Dmitry Denisenko, John Freeman, Michael Kinsner, David Neto, Jason Wong, Peter Yiannacouras, Deshanand P. Singh |
| 2011 | FPGA | Line-level incremental resynthesis techniques for FPGAs. | Doris Chen, Deshanand P. Singh |
| 2010 | FPGA | A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs. | Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz |
| 2010 | FPL | Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs). | Doris Chen, Deshanand P. Singh |
| 2006 | ICCAD | Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. | Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown |
| 2005 | DAC | FPGA technology mapping: a study of optimality. | Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown |
| 2005 | DAC | Incremental retiming for FPGA physical synthesis. | Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown |
| 2005 | FPL | FPGA PLB Evaluation using Quantified Boolean Satisfiability. | Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown |
| 2005 | FPL | Post-Placement BDD-Based Decomposition for FPGAs. | Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown |
| 2005 | SAT | FPGA Logic Synthesis Using Quantified Boolean Satisfiability. | Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown |
| 2002 | FPGA | Integrated retiming and placement for field programmable gate arrays. | Deshanand P. Singh, Stephen Dean Brown |
| 2002 | FPGA | Constrained clock shifting for field programmable gate arrays. | Deshanand P. Singh, Stephen Dean Brown |
| 2002 | ICCAD | Incremental placement for layout driven optimizations on FPGAs. | Deshanand P. Singh, Stephen Dean Brown |
| 2001 | FPGA | The case for registered routing switches in field programmable gate arrays. | Deshanand P. Singh, Stephen Dean Brown |