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Diana Ghringer

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

41

Venues

12

Active years

2008–2026

Best venue rank

A*

Where they publish

Papers

41 indexed papers, newest first.

YearVenueTitleAuthors
2026ISCASA RISC-V Coprocessor to Accelerate Structured Sparse-Dense Matrix Multiplications.Rohan Krishna Vijayaraghavan, Ahmed Kamaleldin, Pruthul Pradeep Andy, Diana Ghringer
2026ISCASMoSim: A Modular Simulation Framework for FPGA-based Systolic CNN Accelerators.Jin Yuan, Zuwen Ou, Guangjin Li, Ahmed Kamaleldin, Diana Ghringer
2025DSDHardware-Level Adaptive Scheduling for Reconfigurable Accelerators on Virtualized FPGAs.Lu Jiang, Zuwen Ou, Diana Ghringer
2025DSDTowards an Energy-Efficient RISC-V Core Architecture with Dynamic Dual-Issue and Clock Gating.Ahmad Othman, Hueseyin Ege Pamuk, Ahmed Kamaleldin, Diana Ghringer
2025FPLTowards Instruction-Controlled In-Pipeline GEMM Acceleration in a Dual-Issue RISC-V Core for Edge Applications.Ahmad Othman, Darmen Ilyas, Ahmed Kamaleldin, Diana Ghringer
2024DSDDA-CGRA: Domain-Aware Heterogeneous Coarse-Grained Reconfigurable Architecture for the Edge.Ensieh Aliagha, Najdet Charaf, Nitin Krishna Venkatesan, Diana Ghringer
2024DSDHardware-level Access Control and Scheduling of Shared Hardware Accelerators.Cornelia Wulf, Sergio A. Pertuz, Diana Ghringer
2024FPLEnergy-Aware Synchronization of Hardware Tasks in Virtualized Embedded Systems.Cornelia Wulf, Gkhan Akgn, Mehdi Safarpour, Anastacia Grishchenko, Diana Ghringer
2024WCNCIndoor THz N-LoS Communication and Radar Sensing Through Wall Reflections.Aman Batra, Fawad Sheikh, Michael Wiemeler, Diana Ghringer, Thomas Kaiser
2023DSDInvestigating the Impact of Non-Volatile Memories on Energy-Efficiency of Coarse-Grained Reconfigurable Architectures.Ensieh Aliagha, Veronia Iskandar, Stephan Enseleit, Diana Ghringer
2023DSDRTASS: a RunTime Adaptable and Scalable System for Network-on-Chip-Based Architectures.Najdet Charaf, Julian Haase, Adrian Kulisch, Christian von Elm, Diana Ghringer
2023DSDVirtualization of Hardware Accelerators in a Network-on-Chip.Cornelia Wulf, Julian Haase, Matthias Nickel, Diana Ghringer
2022FPLA Framework for Intrinsic Evolvable Systems.Najdet Charaf, Diana Ghringer
2022FPLA Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore Systems.Ahmed Kamaleldin, Diana Ghringer
2022FPLModel-based Generation of Hardware/Software Architectures for Robotics Systems.Ariel Podlubne, Johannes Mey, Sergio A. Pertuz, Uwe Amann, Diana Ghringer
2022FPLVirtualization of Reconfigurable Mixed-Criticality Systems.Cornelia Wulf, Najdet Charaf, Diana Ghringer
2022FPLVirtualization of Embedded Reconfigurable Systems.Cornelia Wulf, Diana Ghringer
2022PDPGraphCL: A Framework for Execution of Data-Flow Graphs on Multi-Device Platforms.Konrad Moren, Diana Ghringer
2021FPLPower-Aware Computing Systems on FPGAs: A Survey.Gkhan Akgn, Muhammad Ali, Diana Ghringer
2021FPLPower-Aware Real-Time Operating Systems on Reconfigurable Architectures.Gkhan Akgn, Diana Ghringer
2021FPLDesign For Agility: A Modular Reconfigurable Platform for Heterogeneous Many-Core Architectures.Ahmed Kamaleldin, Diana Ghringer
2021FPLReconfigurable Computing Systems as Component-oriented Designs for Robotics.Ariel Podlubne, Diana Ghringer
2021FPLWormhole Computing in Networks-on-Chip.Jens Rettkowski, Diana Ghringer
2021FPLA Survey on Hypervisor-based Virtualization of Embedded Reconfigurable Systems.Cornelia Wulf, Michael Willig, Diana Ghringer
2021MICROPerformance analysis of application-specific instruction-set routers in networks-on-chip.Jens Rettkowski, Julian Haase, Sven Primus, Michael Hbner, Diana Ghringer
2021PDPA Cross-Platform OpenVX Library for FPGA Accelerators.Maria Anglica Dvila-Guzmn, Ruben Gran Tejero, Mara Villarroya-Gaud, Daro Surez Gracia, Lester Kalms, Diana Ghringer
2020PDPCoopCL: Cooperative Execution of OpenCL Programs on Heterogeneous CPU-GPU Platforms.Konrad Moren, Diana Ghringer
2019FPLEfficient Pattern Recognition Algorithm Including a Fast Retina Keypoint FPGA Implementation.Lester Kalms, Maximilian Hajduk, Diana Ghringer
2018FPLCycle-Accurate and Cycle-Reproducible Debugging of Embedded Designs Using Artificial Intelligence.Habib ul Hasan Khan, Diana Ghringer
2018ICCSAutomatic Mapping for OpenCL-Programs on CPU/GPU Heterogeneous Platforms.Konrad Moren, Diana Ghringer
2017FPLExploration of OpenCL for FPGAs using SDAccel and comparison to GPUs and multicore CPUs.Lester Kalms, Diana Ghringer
2016DATEComputation and communication challenges to deploy robots in assisted living environments.Georgios Keramidas, Christos P. Antonopoulos, Nikolaos S. Voros, Fynn Schwiegelshohn, Philipp Wehner, Jens Rettkowski, Diana Ghringer, Michael Hbner, Stasinos Konstantopoulos, Theodoros Giannakopoulos, Vangelis Karkaletsis, Vaggelis Mariatos
2015EUCA Holistic Approach for Advancing Robots in Ambient Assisted Living Environments.Fynn Schwiegelshohn, Philipp Wehner, Jens Rettkowski, Diana Ghringer, Michael Hbner, Georgios Keramidas, Christos P. Antonopoulos, Nikolaos S. Voros
2014ISPAFuture Trends on Adaptive Processing Systems.Benedikt Janen, Jones Yudi Mori, Osvaldo Navarro, Diana Ghringer, Michael Hbner
2012DATEVirtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems.Stephan Werner, Oliver Oey, Diana Ghringer, Michael Hbner, Jrgen Becker
2012DSDFrom Scilab to High Performance Embedded Multicore Systems: The ALMA Approach.Jrgen Becker, Timo Stripf, Oliver Oey, Michael Hbner, Steven Derrien, Daniel Mnard, Olivier Sentieys, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Kostas Masselos, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Dimitrios Kritharidis, Nikolaos Mitas, Diana Ghringer
2011FPLRAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC.Diana Ghringer, Stephan Werner, Michael Hbner, Jrgen Becker
2010FCCMA Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip.Diana Ghringer, Michael Hbner, Michael Benz, Jrgen Becker
2010FPGAA semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only).Diana Ghringer, Michael Hbner, Michael Benz, Jrgen Becker
2009FPLStar-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol.Diana Ghringer, Bin Liu, Michael Hbner, Jrgen Becker
2008FPLNew dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach.Diana Ghringer, Michael Hbner, Thomas Perschke, Jrgen Becker