Edoardo Fusella
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
4
Active years
2013–2018
Best venue rank
A
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | DATE | Understanding turn models for adaptive routing: The modular approach. | Edoardo Fusella, Alessandro Cilardo |
| 2017 | AINA | A Deterministic Approach to Improve Inter-Domain Parallelism of Clustered MPSoC Interconnects. | Edoardo Fusella |
| 2016 | DATE | PhoNoCMap: An application mapping tool for photonic networks-on-chip. | Edoardo Fusella, Alessandro Cilardo |
| 2015 | FPL | Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip. | Edoardo Fusella, Alessandro Cilardo, Antonino Mazzeo |
| 2015 | HPCC | Crosstalk-Aware Mapping for Tile-Based Optical Network-on-Chip. | Edoardo Fusella, Alessandro Cilardo |
| 2014 | DATE | Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems. | Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo |
| 2013 | FPL | Automated synthesis of FPGA-based heterogeneous interconnect topologies. | Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo |