| 2021 | EDUCON | Microelectronics Education Environment: A Training Model for the Semiconductors Market. | Raphael R. N. Souza, Agord M. P. Jnior, Herclio M. Cavalcanti, Eduardo R. de Lima, Leandro Tiago Manra |
| 2018 | PIMRC | A Low Complexity ICFO Estimator and Compensator for IEEE 802.15.4g MR-OFDM PHY: Algorithm Proposal and Hardware Implementation. | Denise C. Alves-Tamagno, Eduardo R. de Lima, Renato Rocha Lopes |
| 2016 | GLOBECOM | Algorithm and Digital Circuit for Blind Frequency and Band Estimation in Spans with Multiple Signals. | Jos A. Bianco Filho, Cesar G. Chaves, Eduardo R. de Lima, Lus Geraldo P. Meloni |
| 2016 | ISCAS | Architecture design and implementation of key components of an OFDM transceiver for IEEE 802.15.4g. | Denise C. Alves, Gabriel S. da Silva, Eduardo R. de Lima, Cesar G. Chaves, Daniel Urdaneta, Tiago D. Perez, Maique C. Garcia |
| 2016 | PIMRC | Using maximal ratio combining and subcarrier selection to improve the OFDM receiver performance in IEEE802.15.4g. | Gabriel S. da Silva, Eduardo R. de Lima, Cesar G. Chaves |
| 2015 | ISCAS | A novel fine frequency estimation serial architecture applied in satellite communications. | Gabriel S. da Silva, Augusto F. R. Queiroz, Eduardo R. de Lima, Cesar G. Chaves |
| 2004 | FPL | Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2. | Ma Jos Canet, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat, Eduardo R. de Lima |
| 2004 | PIMRC | A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems. | Ma Jos Canet, Felip Vicedo, Vicen Almenar, Javier Valls, Eduardo R. de Lima |