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Edward J. McCluskey

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

116

Venues

13

Active years

1961–2008

Best venue rank

A*

Where they publish

Papers

116 indexed papers, newest first.

YearVenueTitleAuthors
2008ITCFailing Frequency Signature Analysis.Jaekwang Lee, Edward J. McCluskey
2008ITCLaunch-on-Shift-Capture Transition Tests.Intaik Park, Edward J. McCluskey
2008VTSHow Many Test Patterns are Useless?Franois-Fabien Ferhani, Nirmal R. Saxena, Edward J. McCluskey, Phil Nigh
2008VTSError Sequence Analysis.Jaekwang Lee, Intaik Park, Edward J. McCluskey
2008VTSInconsistent Fail due to Limited Tester Timing Accuracy.Intaik Park, Donghwi Lee, Erik Chmelar, Edward J. McCluskey
2007ITCCalifornia scan architecture for high quality and low power testing.Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey
2007VTSTest Set Reordering Using the Gate Exhaustive Test Metric.Kyoung Youn Cho, Edward J. McCluskey
2006ITCClassifying Bad Chips and Ordering Test Sets.Franois-Fabien Ferhani, Edward J. McCluskey
2006VTSSession Abstract.Erik Chmelar, Edward J. McCluskey
2005ITCGate exhaustive testing.Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey
2005VTSEffective TARO Pattern Generation.Intaik Park, Ahmad A. Al-Yamani, Edward J. McCluskey
2004ITCSpeed Clustering of Integrated Circuits.Kenneth A. Brand, Erik H. Volkerink, Edward J. McCluskey, Subhasish Mitra
2004VTSELF-Murphy Data on Defects and Test Sets.Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, Franois-Fabien Ferhani, Edward Li, Subhasish Mitra
2004VTSDelay Defect Screening using Process Monitor Structures.Subhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger
2004VTSA Multi-Configuration Strategy for an Application Dependent Testing of FPGAs.Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure
2003DACSeed encoding with LFSRs and cellular automata.Ahmad A. Al-Yamani, Edward J. McCluskey
2003VTSBuilt-In Reseeding for Serial Bist.Ahmad A. Al-Yamani, Edward J. McCluskey
2003VTSBist Reseeding with very few Seeds.Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey
2002ITCFault Grading FPGA Interconnect Test Configurations.Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey
2002VTSDiagnosis of Sequence-Dependent Chips.Chien-Mo James Li, Edward J. McCluskey
2002VTSDebating the Future of Burn-In.Edward J. McCluskey, Subhasish Mitra, Bob Madge, Peter C. Maxwell, Phil Nigh, Mike Rodgers
2002VTSDesign for Testability and Testing of IEEE 1149.1 Tap Controller.Subhasish Mitra, Edward J. McCluskey, Samy Makar
2002VTSExperimental Results for Slow-Speed Testing.Chao-Wen Tseng, James Li, Edward J. McCluskey
2001DSNTechniques for Estimation of Design Diversity for Combinational Logic Circuits.Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
2001FCCMColumn-Based Precompiled Configuration Techniques for FPGA.Wei-Je Huang, Edward J. McCluskey
2001FPGAA memory coherence technique for online transient error recovery of FPGA configurations.Wei-Je Huang, Edward J. McCluskey
2001ITCTesting for resistive opens and stuck opens.Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey
2001ITCMultiple-output propagation transition fault test.Chao-Wen Tseng, Edward J. McCluskey
2001ITCOn-line testing and recovery in TMR systems for real-time applications.Shu-Yi Yu, Edward J. McCluskey
2001VTSDiagnosis of Tunneling Opens.Chien-Mo James Li, Edward J. McCluskey
2001VTSDesign Diversity for Concurrent Error Detection in Sequential Logic Circuts.Subhasish Mitra, Edward J. McCluskey
2001VTSDesign of Redundant Systems Protected Against Common-Mode Failures.Subhasish Mitra, Edward J. McCluskey
2001VTSMINVDD Testing for Weak CMOS ICs.Chao-Wen Tseng, Ray Chen, Edward J. McCluskey, Phil Nigh
2001VTSAn Evaluation of Pseudo Random Testing for Detecting Real Defects.Chao-Wen Tseng, Subhasish Mitra, Edward J. McCluskey, Scott Davidson
2000FCCMA Reliable LZ Data Compressor on Reconfigurable Coprocessors.Wei-Je Huang, Nirmal R. Saxena, Edward J. McCluskey
2000FCCMAn ACS Robotic Control Algorithm with Fault Tolerant Capabilities.Shu-Yi Yu, Nirmal R. Saxena, Edward J. McCluskey
2000ITCTesting for tunneling opens.Chien-Mo James Li, Edward J. McCluskey
2000ITCStuck-fault tests vs. actual defects.Edward J. McCluskey, Chao-Wen Tseng
2000ITCCombinational logic synthesis for diversity in duplex systems.Subhasish Mitra, Edward J. McCluskey
2000ITCWhich concurrent error detection scheme to choose ?Subhasish Mitra, Edward J. McCluskey
2000PRDCTransient errors and rollback recovery in LZ compression.Wei-Je Huang, Edward J. McCluskey
2000VTSWord Voter: A New Voter Design for Triple Modular Redundant Systems.Subhasish Mitra, Edward J. McCluskey
2000VTSFault Escapes in Duplex Systems.Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
2000VTSCold Delay Defect Screening.Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao, David M. Wu
1999ITCA design diversity metric and reliability analysis for redundant systems.Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
1999ITCFinite state machine synthesis with concurrent error detection.Chaohuang Zeng, Nirmal R. Saxena, Edward J. McCluskey
1999VTSPADded Cache: A New Fault-Tolerance Technique for Cache Memories.Philip P. Shirvani, Edward J. McCluskey
1998ITCDetecting resistive shorts for CMOS domino circuits.Jonathan T.-Y. Chang, Edward J. McCluskey
1998ITCAnalysis of pattern-dependent and timing-dependent failures in an experimental test chip.Jonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey
1998SMCDependable adaptive computing systems-the ROAR project.Nirmal R. Saxena, Edward J. McCluskey
1998VTSExperimental Results for IDDQ and VLV Testing.Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu, Sanjay Wattal, Mike Purtell, Edward J. McCluskey
1997ICCADAn output encoding problem and a solution technique.Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
1997ICCDPseudo-Random Pattern Testing of Bridging Faults.Nur A. Touba, Edward J. McCluskey
1997ITCScan Synthesis for One-Hot Signals.Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
1997VTSSHOrt voltage elevation (SHOVE) test for weak CMOS ICs.Jonathan T.-Y. Chang, Edward J. McCluskey
1997VTSATPG for scan chain latches and flip-flops.Samy Makar, Edward J. McCluskey
1997VTSHigh-Level Synthesis for Orthogonal Sca.Robert B. Norwood, Edward J. McCluskey
1996ITCDetecting Delay Flaws by Very-Low-Voltage Testing.Jonathan T.-Y. Chang, Edward J. McCluskey
1996ITCAnalysis and Detection of Timing Failures in an Experimental Test Chip.Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin Chu, Sanjay Wattal, Edward J. McCluskey, Robert L. Stokes, William D. Farwell
1996ITCOrthogonal Scan: Low-Overhead Scan for Data Paths.Robert B. Norwood, Edward J. McCluskey
1996ITCAltering a Pseudo-Random Bit Sequence for Scan-Based BIST.Nur A. Touba, Edward J. McCluskey
1996VTSQuantitative analysis of very-low-voltage testing.Jonathan T.-Y. Chang, Edward J. McCluskey
1996VTSSynthesis-for-scan and scan chain ordering.Robert B. Norwood, Edward J. McCluskey
1996VTSTest point insertion based on path tracing.Nur A. Touba, Edward J. McCluskey
1996VTSApplying two-pattern tests using scan-mapping.Nur A. Touba, Edward J. McCluskey
1995ITCAn Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design.Piero Franco, William D. Farwell, Robert L. Stokes, Edward J. McCluskey
1995ITCAn Experimental Chip to Evaluate Test Techniques: Experiment Results.Siyad C. Ma, Piero Franco, Edward J. McCluskey
1995ITCFunctional Tests for Scan Chain Latches.Samy Makar, Edward J. McCluskey
1995ITCSynthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST.Nur A. Touba, Edward J. McCluskey
1995VTSChecking experiments to test latches.Samy Makar, Edward J. McCluskey
1995VTSAn apparatus for pseudo-deterministic testing.Shridhar K. Mukund, Edward J. McCluskey, T. R. N. Rao
1995VTSTransformed pseudo-random patterns for BIST.Nur A. Touba, Edward J. McCluskey
1994ICCADLogic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection.Nur A. Touba, Edward J. McCluskey
1994ITCAutomated Logic Synthesis of Random-Pattern-Testable Circuits.Nur A. Touba, Edward J. McCluskey
1994VTSOn-line delay testing of digital circuits.Piero Franco, Edward J. McCluskey
1994VTSThree-pattern tests for delay faults.Piero Franco, Edward J. McCluskey
1994VTSOpen faults in BiCMOS gates.Siyad C. Ma, Edward J. McCluskey
1993ITCSynthesizing for Scan Dependence in Built-In Self-Testable Desings.LaNae J. Avra, Edward J. McCluskey
1993ITCVery-Low-Voltage Testing for Weak CMOS Logic ICs.Hong Hao, Edward J. McCluskey
1993ITCQuality and Single-Stuck Faults.Edward J. McCluskey
1992ITCNon-Conventional Faults in BiCMOS Digital Circuits.Siyad C. Ma, Edward J. McCluskey
1991ITCDelay Testing of Digital Circuits by Output Waveform Analysis.Piero Franco, Edward J. McCluskey
1991ITCTwo-Pattern Test Capabilities of Autonomous TPG Circuits.Kiyoshi Furuya, Edward J. McCluskey
1991ITC"Resistive Shorts" Within CMOS Gates.Hong Hao, Edward J. McCluskey
1991ITCRefined Bounds on Signature Analysis Aliasing for Random Testing.Nirmal R. Saxena, Piero Franco, Edward J. McCluskey
1990ITCDiagnosing CMOS bridging faults with stuck-at fault dictionaries.Steven D. Millman, Edward J. McCluskey, John M. Acken
1989ICCADThe critical path for multiple faults.Samy Makar, Edward J. McCluskey
1989ICCADArithmetic and galois checksums.Nirmal R. Saxena, Edward J. McCluskey
1988ITCOn the Testing of Multiplexers.Samy Makar, Edward J. McCluskey
1988ITCPractice and Theory.Edward J. McCluskey
1988ITCIC Quality and Test Transparency.Edward J. McCluskey, Fred Buelow
1988ITCDetecting Bridging Faults with Stuck-at Test Sets.Steven D. Millman, Edward J. McCluskey
1988ITCOn Benchmarking Digital Testing Systems.Samiha Mourad, Edward J. McCluskey
1988ITCPartial Hardware Partitioning: A New Pseudo-Exhaustive Test Implementation.Jon G. Udeli Jr., Edward J. McCluskey
1987ICDEModeling the Effect of Chip Failures on Cache Memory Systems.Hassanein H. Amer, Edward J. McCluskey
1986ITCAn Experiment on Intermittent-Failure Mechanisms.Mario Lcio Crtes, Edward J. McCluskey
1986ITCTwo CMOS Metastability Sensors.Greg G. Freeman, Dick L. Liu, Bruce A. Wooley, Edward J. McCluskey
1986ITCMultiple Stuck-At Fault Coverage of Single Stuck-At Fault Test Sets.Joseph L. A. Hughes, Edward J. McCluskey
1986ITCCircuits for Pseudo-Exhaustive Test Pattern Generation.Laung-Terng Wang, Edward J. McCluskey
1986ITCA Hybrid Design of Maximum-Length Sequence Generators.Laung-Terng Wang, Edward J. McCluskey
1985ITCTest Length for Pseudo Random Testing.Cary K. Chin, Edward J. McCluskey
1985ITCConcurrent System-Level Error Detection Using a Watchdog Processor.Aamer Mahmood, Edward J. McCluskey, Aydin Ersoz
1985ITCTest Teaching.Edward J. McCluskey
1984ITCLower Overhead Design for Testability of Programmable Logic Arrays.Saied Bozorgui-Nesbat, Edward J. McCluskey
1984ITCPseudo-Exhaustive Testing of Sequential Machines Using Signature Analysis.Syed Zahoor Hassan, Edward J. McCluskey
1984ITCAn Analysis of the Multiple Fault Detection Capabilities of Single Stuck-at Fault Test Sets.Joseph L. A. Hughes, Edward J. McCluskey
1983ITCConcurrent Fault Detection Using a Watchdog Processor and Assertions.Aamer Mahmood, Edward J. McCluskey, David J. Lu
1983ITCTeaching Testing.Edward J. McCluskey
1983ITCRecurrent Test Patterns.Edward J. McCluskey, David J. Lu
1982DACVerification testing.Edward J. McCluskey
1982ITCBuilt-In Verification Test.Edward J. McCluskey
1980RTSSSummary of Structural integrity Checking.David J. Lu, Edward J. McCluskey, Masood Namjoo
1964FOCSDerivation of optimum test sequences for sequential machinesJ. F. Poage, Edward J. McCluskey
1963FOCSLogical design theory of NOR gate networks with no complemented inputsEdward J. McCluskey
1962FOCSReduction of feedback loops in sequential circuits and carry leads in iterative networksEdward J. McCluskey
1961FOCSMinimal sums for Boolean functions having many unspecified fundamental productsEdward J. McCluskey