| 2018 | ISPDC | STP - A Quadratic VLSI Placement Tool Using Graphic Processing Units. | Bjorn Bredthauer, Markus Olbrich, Erich Barke |
| 2016 | DATE | Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis. | Erich Barke, Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Eckhard Hennig, Hyun-Sek Lukas Lee, Wolfgang Nebel, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher |
| 2015 | ASPDAC | Automated generation of hybrid system models for reachability analysis of nonlinear analog circuits. | Hyun-Sek Lukas Lee, Matthias Althoff, Stefan Hoelldampf, Markus Olbrich, Erich Barke |
| 2014 | DATE | Application of Mission Profiles to enable cross-domain constraint-driven design. | C. Katzschke, M.-P. Sohn, Markus Olbrich, Volker Meyer zu Bexten, Markus Tristl, Erich Barke |
| 2011 | ICCAD | A theoretical probabilistic simulation framework for dynamic power estimation. | Lei Wang, Markus Olbrich, Erich Barke, Thomas Bchner, Markus Bhler, Philipp V. Panitz |
| 2011 | ICCD | Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulation. | Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke |
| 2011 | VLSID | A Statistical Learning Based Modeling Approach and Its Application in Leakage Library Characterization. | Min Zhang, R. Huler, Markus Olbrich, Harald Kinzelbach, Erich Barke |
| 2010 | FDL | Towards Abstract Analysis Techniques for Range Based System Simulations. | Florian Schupfer, Christoph Grimm, Markus Olbrich, Michael Krgel, Erich Barke |
| 2010 | FDL | An Accelerated Mixed-Signal Simulation Kernel for SystemC. | Daniel Zaum, Stefan Hoelldampf, Markus Olbrich, Erich Barke, Ingmar Neumann |
| 2009 | DATE | Formal approaches to analog circuit verification. | Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang |
| 2008 | ASPDAC | Analog circuit simulation using range arithmetics. | Darius Grabowski, Markus Olbrich, Erich Barke |
| 2008 | ASPDAC | Distribution arithmetic for stochastical analysis. | Markus Olbrich, Erich Barke |
| 2008 | DATE | Determining the Technical Complexity of Integrated Circuits. | Peter Leppelt, Erich Barke |
| 2008 | DDECS | A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles. | Thomas Jambor, Daniel Zaum, Markus Olbrich, Erich Barke |
| 2008 | FDL | Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). | Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt |
| 2007 | DAC | Efficient Modeling Techniques for Dynamic Voltage Drop Analysis. | Hedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke |
| 2007 | DATE | CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. | Min Zhang, Markus Olbrich, David Seider, Martin Frerichs, Harald Kinzelbach, Erich Barke |
| 2007 | FDL | Range Arithmetics to Speed up Reachability Analysis of Analog Systems. | Darius Grabowski, Markus Olbrich, Christoph Grimm, Erich Barke |
| 2007 | FPL | Incremental Fault Emulation. | Jan Torben Weinkopf, Klaus Harbich, Erich Barke |
| 2006 | FDL | Using Sequential Equations to Improve Efficiency and Robustness. | Daniel Platte, Shangjing Jing, Ralf Sommer, Erich Barke |
| 2006 | FPL | Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models. | Jan Torben Weinkopf, Klaus Harbich, Erich Barke |
| 2006 | ISCAS | Semi-symbolic modeling and simulation of circuits and systems. | Darius Grabowski, Christoph Grimm, Erich Barke |
| 2004 | DATE | Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. | Lutz Nthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke |
| 2004 | DATE | Placement Using a Localization Probability Model (LPM). | Markus Olbrich, Erich Barke |
| 2002 | CAV | On Discrete Modeling and Model Checking for Nonlinear Analog Systems. | Walter Hartong, Lars Hedrich, Erich Barke |
| 2002 | DAC | Model checking algorithms for analog verification. | Walter Hartong, Lars Hedrich, Erich Barke |
| 2002 | DATE | A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs . | Joerg Abke, Erich Barke |
| 2002 | DATE | An Approach to Model Checking for Nonlinear Analog Systems. | Walter Hartong, Lars Hedrich, Erich Barke |
| 2002 | DATE | Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. | Ralf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke |
| 2002 | ICCAD | Analog circuit sizing based on formal methods using affine arithmetic. | Andreas C. Lemke, Lars Hedrich, Erich Barke |
| 2002 | VLSID | An Upper Bound for 3D Slicing Floorplans. | Silke Salewski, Erich Barke |
| 2001 | DATE | Architecture driven partitioning. | Joachim Kter, Erich Barke |
| 2001 | DATE | An improved hierarchical classification algorithm for structural analysis of integrated circuits. | Markus Olbrich, Achim Rein, Erich Barke |
| 2001 | FPL | A New Placement Method for Direct Mapping into LUT-Based FPGAs. | Joerg Abke, Erich Barke |
| 2001 | FPL | PuMA++: From Behavioral Specification to Multi-FPGA-Prototype. | Klaus Harbich, Erich Barke |
| 2000 | DAC | A current driven routing and verification methodology for analog applications. | Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke |
| 2000 | DATE | Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications. | Thorsten Adler, Erich Barke |
| 2000 | DATE | Static Timing Analysis Taking Crosstalk into Account. | Matthias Ringe, Thomas Lindenkreuz, Erich Barke |
| 2000 | FPL | CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs. | Joerg Abke, Erich Barke |
| 1999 | RSP | A Universal Module Generator for LUT-Based FPGAs. | Joerg Abke, Erich Barke, Jrn Stohmann |
| 1999 | RSP | A Case Study: Logic Emulation - Pitfalls and Solutions. | Klaus Harbich, Jrn Stohmann, Erich Barke, Ludwig Schwoerer |
| 1998 | ASPDAC | Real Time Fault Injection Using Logic Emulators. | Reza Sedaghat-Maman, Erich Barke |
| 1998 | DATE | A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. | Lars Hedrich, Erich Barke |
| 1998 | DATE | Path Verification Using Boolean Satisfiability. | Matthias Ringe, Thomas Lindenkreuz, Erich Barke |
| 1998 | FPL | An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping. | Jrn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke |
| 1997 | ASPDAC | Design driven partitioning. | Dirk Behrens, Erich Barke, Robert Tolkiehn |
| 1997 | ICCD | A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs. | Jrn Stohmann, Erich Barke |
| 1997 | RSP | A new approach to fault emulation. | Reza Sedaghat-Maman, Erich Barke |
| 1996 | DAC | Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. | Carsten Borchers, Lars Hedrich, Erich Barke |
| 1996 | DATE | PALACE: A Parallel and Hierarchical Layout Analyzer and Circuit Extractor. | Frank Scherber, Erich Barke, Wolfgang Meier |
| 1996 | FPL | A Universal CLA Adder Generator for SRAM-Based FPGAs. | Jrn Stohmann, Erich Barke |
| 1996 | ICCAD | Hierarchical partitioning. | Dirk Behrens, Klaus Harbich, Erich Barke |
| 1995 | ICCAD | A formal approach to nonlinear analog circuit verification. | Lars Hedrich, Erich Barke |
| 1985 | DAC | Resistance calculation from mask artwork data by finite element method. | Erich Barke |
| 1984 | DAC | A technology independent block extraction algorithm. | F. Luellau, T. Hoepken, Erich Barke |
| 1983 | DAC | A layout verification system for analog bipolar integrated circuits. | Erich Barke |