| 2026 | FPGA | RND: A Mixed-Grained Parallel Routing Framework with Region-based Net Decomposition for UltraScale FPGAs. | Wenhao Lin, Zewen Li, Xinshi Zang, Evangeline F. Y. Young |
| 2025 | DAC | SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding. | Chengxi Li, Yang Sun, Lei Chen, Yiwen Wang, Mingxuan Yuan, Evangeline F. Y. Young |
| 2025 | DAC | Simulation-based Parallel Sweeping: A New Perspective on Combinational Equivalence Checking. | Tianji Liu, Evangeline F. Y. Young |
| 2025 | DATE | Fast Dynamic IR-Drop Prediction with Dual-Path Spatial-Temporal Attention. | Bangqi Fu, Lixin Liu, Qijing Wang, Yutao Wang, Martin D. F. Wong, Evangeline F. Y. Young |
| 2025 | FPL | TRPlaceFPGA-MP: A Two-Stage Reinforcement Learning Framework for Fast FPGA Macro Placer. | Qin Luo, Xinshi Zang, Evangeline F. Y. Young, Martin D. F. Wong |
| 2025 | ICCAD | ExactMap: Enhancing Delay Optimization in Parallel ASIC Technology Mapping. | Zhenxuan Xie, Lixin Liu, Tianji Liu, Evangeline F. Y. Young |
| 2025 | KSEM | POAgent: A Multi-agent Controller Towards Adaptive Parameter Optimization. | Qijing Wang, Martin D. F. Wong, Evangeline F. Y. Young |
| 2024 | ASPDAC | CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs. | Bangqi Fu, Lixin Liu, Yang Sun, Wing Ho Lau, Martin D. F. Wong, Evangeline F. Y. Young |
| 2024 | ASPDAC | FineMap: A Fine-grained GPU-parallel LUT Mapping Engine. | Tianji Liu, Lei Chen, Xing Li, Mingxuan Yuan, Evangeline F. Y. Young |
| 2024 | DAC | GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis. | Shiju Lin, Guannan Guo, Tsung-Wei Huang, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong |
| 2024 | DAC | Size-Optimized Depth-Constrained Large Parallel Prefix Circuits. | Shiju Lin, Bentian Jiang, Weihua Sheng, Evangeline F. Y. Young |
| 2024 | DAC | Massively Parallel AIG Resubstitution. | Yang Sun, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young |
| 2024 | FCCM | A Routability-Driven Ultrascale FPGA Macro Placer with Complex Design Constraints. | Qin Luo, Xinshi Zang, Qijing Wang, Fangzhou Wang, Evangeline F. Y. Young, Martin D. F. Wong |
| 2024 | ICCAD | Hybrid Modeling and Weighting for Timing-driven Placement with Efficient Calibration. | Bangqi Fu, Lixin Liu, Martin D. F. Wong, Evangeline F. Y. Young |
| 2024 | ICCAD | InstantGR: Scalable GPU Parallelization for Global Routing. | Shiju Lin, Liang Xiao, Jinwei Liu, Evangeline F. Y. Young |
| 2024 | ICCAD | Potter: A Parallel Overlap-Tolerant Router for UltraScale FPGAs. | Xinshi Zang, Wenhao Lin, Jinwei Liu, Evangeline F. Y. Young |
| 2023 | ASPDAC | An Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA Systems. | Dan Zheng, Evangeline F. Y. Young |
| 2023 | DAC | EDGE: Efficient DAG-based Global Routing Engine. | Jinwei Liu, Evangeline F. Y. Young |
| 2023 | DAC | Rethinking AIG Resynthesis in Parallel. | Tianji Liu, Evangeline F. Y. Young |
| 2022 | DAC | NovelRewrite: node-level parallel AIG rewriting. | Shiju Lin, Jinwei Liu, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young |
| 2022 | DAC | Xplace: an extremely fast and extensible global placement framework. | Lixin Liu, Bangqi Fu, Martin D. F. Wong, Evangeline F. Y. Young |
| 2022 | DAC | Partition and place finite element model on wafer-scale engine. | Jinwei Liu, Xiaopeng Zhang, Shiju Lin, Xinshi Zang, Jingsong Chen, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young |
| 2022 | DAC | A2-ILT: GPU accelerated ILT with spatial attention mechanism. | Qijing Wang, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young |
| 2022 | ITC | RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement. | Xiaopeng Zhang, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Evangeline F. Y. Young, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao |
| 2021 | ASPDAC | Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method. | Haoyu Yang, Shifan Zhang, Kang Liu, Siting Liu, Benjamin Tan, Ramesh Karri, Siddharth Garg, Bei Yu, Evangeline F. Y. Young |
| 2021 | ASPDAC | Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment. | Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young |
| 2021 | DAC | REST: Constructing Rectilinear Steiner Minimum Tree via Reinforcement Learning. | Jinwei Liu, Gengjie Chen, Evangeline F. Y. Young |
| 2021 | DAC | Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation. | Xiaopeng Zhang, Haoyu Yang, Evangeline F. Y. Young |
| 2020 | DAC | CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model. | Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young |
| 2020 | ICCAD | PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning. | Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young |
| 2020 | ICCAD | CU.POKer: Placing DNNs on Wafer-Scale Al Accelerator with Optimal Kernel Sizing. | Bentian Jiang, Jingsong Chen, Jinwei Liu, Lixin Liu, Fangzhou Wang, Xiaopeng Zhang, Evangeline F. Y. Young |
| 2020 | ICCAD | Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization. | Bentian Jiang, Lixin Liu, Yuzhe Ma, Hang Zhang, Bei Yu, Evangeline F. Y. Young |
| 2020 | ICCAD | Layout Pattern Generation and Legalization with Generative Learning Models. | Xiaopeng Zhang, James P. Shiely, Evangeline F. Y. Young |
| 2019 | ASPDAC | Detailed routing by sparse grid graph and minimum-area-captured path search. | Gengjie Chen, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang, Evangeline F. Y. Young |
| 2019 | ASPDAC | A fast machine learning-based mask printability predictor for OPC acceleration. | Bentian Jiang, Hang Zhang, Jinglei Yang, Evangeline F. Y. Young |
| 2019 | DAC | MARCH: MAze Routing Under a Concurrent and Hierarchical Scheme for Buses. | Jingsong Chen, Jinwei Liu, Gengjie Chen, Dan Zheng, Evangeline F. Y. Young |
| 2019 | DAC | FIT: Fill Insertion Considering Timing. | Bentian Jiang, Xiaopeng Zhang, Ran Chen, Gengjie Chen, Peishan Tu, Wei Li, Evangeline F. Y. Young, Bei Yu |
| 2019 | DAC | Attacking Split Manufacturing from a Deep Learning Perspective. | Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu |
| 2019 | DATE | Dim Sum: Light Clock Tree by Small Diameter Sum. | Gengjie Chen, Evangeline F. Y. Young |
| 2019 | ICCAD | Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction. | Haocheng Li, Gengjie Chen, Bentian Jiang, Jingsong Chen, Evangeline F. Y. Young |
| 2019 | ICCAD | Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. | Chak-Wa Pui, Evangeline F. Y. Young |
| 2018 | ASPDAC | A two-step search engine for large scale boolean matching under NP3 equivalence. | Chak-Wa Pui, Peishan Tu, Haocheng Li, Gengjie Chen, Evangeline F. Y. Young |
| 2018 | DAC | Routability-driven and fence-aware legalization for mixed-cell-height circuits. | Haocheng Li, Wing-Kai Chow, Gengjie Chen, Evangeline F. Y. Young, Bei Yu |
| 2018 | DAC | GAN-OPC: mask optimization with lithography-guided generative adversarial nets. | Haoyu Yang, Shuhe Li, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young |
| 2018 | FCCM | Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. | Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F. Y. Young, Zhiru Zhang |
| 2017 | DAC | Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond. | Jian Kuang, Evangeline F. Y. Young |
| 2017 | DAC | Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design. | Gengjie Chen, Jian Kuang, Zhiliang Zeng, Hang Zhang, Evangeline F. Y. Young, Bei Yu |
| 2017 | DAC | Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning. | Haoyu Yang, Jing Su, Yi Zou, Bei Yu, Evangeline F. Y. Young |
| 2017 | ICCAD | SALT: Provably good routing topology by a novel steiner shallow-light tree algorithm. | Gengjie Chen, Peishan Tu, Evangeline F. Y. Young |
| 2017 | ICCAD | Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). | Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu |
| 2016 | ASPDAC | Simultaneous template optimization and mask assignment for DSA with multiple patterning. | Jian Kuang, Junjie Ye, Evangeline F. Y. Young |
| 2016 | DAC | Legalization algorithm for multiple-row height standard cell design. | Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young |
| 2016 | DATE | Optimization for Multiple Patterning Lithography with cutting process and beyond. | Jian Kuang, Evangeline F. Y. Young |
| 2016 | ICCAD | Incorporating cut redistribution with mask assignment to enable 1D gridded design. | Jian Kuang, Evangeline F. Y. Young, Bei Yu |
| 2016 | ICCAD | RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs. | Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu |
| 2016 | ICCAD | Enabling online learning in lithography hotspot detection with information-theoretic feature optimization. | Hang Zhang, Bei Yu, Evangeline F. Y. Young |
| 2015 | DATE | A robust approach for process variation aware mask optimization. | Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young |
| 2015 | DATE | An effective triple patterning aware grid-based detailed routing approach. | Zhiqing Liu, Chuangwen Liu, Evangeline F. Y. Young |
| 2014 | ASPDAC | Structural planning of 3D-IC interconnects by block alignment. | Johann Knechtel, Evangeline F. Y. Young, Jens Lienig |
| 2014 | ASPDAC | General purpose cross-referencing Microfluidic Biochip with reduced pin-count. | Jackson H. C. Yeung, Evangeline F. Y. Young |
| 2014 | FPGA | A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only). | Ka-Chun Lam, Wai-Chung Tang, Evangeline F. Y. Young |
| 2014 | ICCAD | Triple patterning lithography aware optimization for standard cell based design. | Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young |
| 2014 | ICCAD | Overlapping-aware throughput-driven stencil planning for E-beam lithography. | Jian Kuang, Evangeline F. Y. Young |
| 2014 | ISCAS | Reducing pin count on cross-referencing Digital Microfluidic Biochip. | Ho Chuen Jackson Yeung, Evangeline F. Y. Young, Chiu-sing Choy |
| 2013 | DAC | Ripple 2.0: high quality routability-driven placement via global router integration. | Xu He, Tao Huang, Wing-Kai Chow, Jian Kuang, Ka-Chun Lam, Wenzan Cai, Evangeline F. Y. Young |
| 2013 | DAC | An efficient layout decomposition approach for triple patterning lithography. | Jian Kuang, Evangeline F. Y. Young |
| 2012 | ICCAD | Construction of rectilinear Steiner minimum trees with slew constraints over obstacles. | Tao Huang, Evangeline F. Y. Young |
| 2011 | ASPDAC | A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing. | Qiang Ma, Hui Kong, Martin D. F. Wong, Evangeline F. Y. Young |
| 2011 | DAC | An exact algorithm for the construction of rectilinear Steiner minimum trees among complex obstacles. | Tao Huang, Evangeline F. Y. Young |
| 2011 | DAC | An optimal algorithm for layer assignment of bus escape routing on PCBs. | Qiang Ma, Evangeline F. Y. Young, Martin D. F. Wong |
| 2011 | FPGA | A monte-carlo floating-point unit for self-validating arithmetic. | Jackson H. C. Yeung, Evangeline F. Y. Young, Philip Heng Wai Leong |
| 2011 | ICCAD | Ripple: An effective routability-driven placer by iterative cell movement. | Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui, Evangeline F. Y. Young |
| 2010 | ASPDAC | A dual-MST approach for clock network synthesis. | Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangeline F. Y. Young |
| 2010 | ASPDAC | Fixed-outline thermal-aware 3D floorplanning. | Linfu Xiao, Subarna Sinha, Jingyu Xu, Evangeline F. Y. Young |
| 2010 | ASPDAC | CrossRouter: a droplet router for cross-referencing digital microfluidic biochips. | Zigang Xiao, Evangeline F. Y. Young |
| 2010 | ICCAD | Obstacle-avoiding rectilinear Steiner minimum tree construction: An optimal approach. | Tao Huang, Evangeline F. Y. Young |
| 2010 | ICCAD | Local clock skew minimization using blockage-aware mixed tree-mesh clock network. | Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, Tao Huang, Haitong Tian, Evangeline F. Y. Young |
| 2010 | ICCAD | Practical placement and routing techniques for analog circuit designs. | Linfu Xiao, Evangeline F. Y. Young, Xiao-Yong He, Kong-Pang Pun |
| 2009 | ASPDAC | Analog placement with common centroid and 1-D symmetry constraints. | Linfu Xiao, Evangeline F. Y. Young |
| 2009 | ICCAD | Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree. | Liang Li, Zaichen Qian, Evangeline F. Y. Young |
| 2008 | ASPDAC | TCG-based multi-bend bus driven floorplanning. | Tilen Ma, Evangeline F. Y. Young |
| 2008 | ICCAD | Obstacle-avoiding rectilinear Steiner tree construction. | Liang Li, Evangeline F. Y. Young |
| 2008 | ICCAD | Network flow-based power optimization under timing constraints in MSV-driven floorplanning. | Qiang Ma, Evangeline F. Y. Young |
| 2007 | ICCAD | Voltage island-driven floorplanning. | Qiang Ma, Evangeline F. Y. Young |
| 2007 | ICCAD | Analog placement with common centroid constraints. | Qiang Ma, Evangeline F. Y. Young, Kong-Pang Pun |
| 2006 | DAC | Optimal cell flipping in placement and floorplanning. | Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu |
| 2006 | ICCAD | Post-placement voltage island generation. | Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu |
| 2006 | ICCAD | Analog placement with symmetry and other placement constraints. | Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu |
| 2005 | ASPDAC | Congestion prediction in floorplanning. | Chiu-Wing Sham, Evangeline F. Y. Young |
| 2003 | ASPDAC | Interconnect-driven floorplanning by searching alternative packings. | Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou |
| 2003 | ASPDAC | Fast buffer planning and congestion optimization in interconnect-driven floorplanning. | Keith W. C. Wong, Evangeline F. Y. Young |
| 2003 | DATE | A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. | Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu |
| 2003 | ICCAD | Retiming with Interconnect and Gate Delay. | Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu |
| 2002 | DATE | Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. | Chris C. N. Chu, Evangeline F. Y. Young |
| 2002 | DATE | Congestion Estimation with Buffer Planning in Floorplan Design. | Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Young |
| 2002 | VLSID | A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. | Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho |