| 2015 | VTS | Signature oriented model pruning to facilitate multi-threaded processors debugging. | Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi |
| 2009 | ICASSP | A cost-error optimized architecture for 9/7 lifting based Discrete Wavelet Transform with balanced pipeline stages. | Alireza Aminlou, Fatemeh Refan, Mahmoud Reza Hashemi, Omid Fatemi, Saeed Safari |
| 2008 | IOLTS | Reliability in Application Specific Mesh-Based NoC Architectures. | Fatemeh Refan, Homa Alemzadeh, Saeed Safari, Paolo Prinetto, Zainalabedin Navabi |
| 2008 | ITC | "Plug & Test" at System Level via Testable TLM Primitives. | Homa Alemzadeh, Stefano Di Carlo, Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi |
| 2007 | ICASSP | A Split Method for Optimized Cost-Quality Hardware Implementation of Lifting-Based Discrete Wavelet Transform. | Alireza Aminlou, Fatemeh Refan, Maryam Homayouni, Omid Fatemi, Mahmoud Reza Hashemi |
| 2007 | ICIP | Two Level Cost-Quality Optimization of 9-7 Lifting-Based Discrete Wavelet Transform. | Alireza Aminlou, Fatemeh Refan, Mahmoud Reza Hashemi, Omid Fatemi |