| 2026 | ISCAS | A 5V swing, 20GS/s, 6-bit Current Steering DAC utilizing LDMOS in 22nm FDSOI CMOS. | Jendrik Kellermann, Urs Hecht, Philipp Nickel, Friedel Gerfers |
| 2026 | ISCAS | An 80 Gbit/s NRZ 100 Gbit/s PAM4 Highly-Efficient Voltage-Mode VCSEL-Driver in 22nm FDSOI CMOS. | Nikolaos Kioulos, Urs Hecht, Helia Ordouei, Nikolay N. Ledentsov, Sebastian Linnhoff, Si-Cong Tian, Friedel Gerfers |
| 2026 | ISCAS | A Highly Efficient Reconfigurable All-Digital DLL-Based RF Transmitter Using Phase Interpolation in 22 nm FDSOI. | Philipp Nickel, Deguang Sun, Robin Staub, Jendrik Kellermann, Andreas Wentzel, Friedel Gerfers |
| 2025 | ISCAS | Halfbex: A RISC-V Microarchitecture with Narrow Data Path for Improved Energy Efficiency. | antas Kesten, Tobias Kaiser, Jenny Lichtenstein, Christian Rudorf, Friedel Gerfers |
| 2025 | ISCAS | A Wideband Open-Loop Residue Amplifier for a 7-bit 10GS/s Two-Step Flash ADC in 22nm SOI CMOS Process. | Jenny Lichtenstein, antas Kesten, Friedel Gerfers |
| 2025 | ISCAS | A Nyquist-rate 128 GS/s 6-Bit 64x Time-Interleaved SAR ADC in 22nm FD-SOI. | Christian Rudorf, Nima Lotfi, Sebastian Linnhoff, Enne Wittenhagen, antas Kesten, Friedel Gerfers |
| 2024 | ISCAS | A mmw Low-Noise Sub-Sampling Phase-Locked Loop with a Non-Pulsed Charge Pump, Frequency Calibration and a Compact Ultra-High-Q Resonator. | Patrick Kurth, Philipp Scholz, Philipp Nickel, Urs Hecht, Enne Wittenhagen, Kai Misselwitz, Friedel Gerfers |
| 2024 | ISCAS | A 16 GS/s Voltage-to-Time Conversion Sampler with 35.9 dB SNDR in 22 nm CMOS FDSOI. | Kai Misselwitz, Friedel Gerfers |
| 2024 | ISCAS | An 11-Bit 12 GS/s Beam-Forming Receiver ADC for a 2x2 Antenna Array utilizing True Time-Delay with 68 dBc SFDR and 55 dB SNDR. | Enne Wittenhagen, Dominik Wilding, Patrick Kurth, Sebastian Linnhoff, Frowin Buballa, Urs Hecht, Patrick J. Artz, Friedel Gerfers |
| 2023 | ETFA | 25Gbps Automotive Ethernet: System PHY Characterization of ESD Based EM Interferences. | Jamila Josip Borda, Friedel Gerfers |
| 2023 | ISCAS | A Charge Pump for Sub-Sampling Phase-Locked Loops with Virtual Reference Frequency Doubling. | Patrick Kurth, Urs Hecht, Frowin Buballa, Sebastian Linnhoff, Helia Ordouei, Friedel Gerfers |
| 2023 | ISCAS | A Digital Pre-Distortion Technique Canceling Code-and Voltage-Dependent Output Impedance Errors in Current-Steering DACs. | Helia Ordouei, Clirim Alija, Patrick Kurth, Friedel Gerfers |
| 2023 | VEHITS | 25Gbps Automotive Ethernet ECU PCB: MDI Design Implementation and Insertion Loss Characterization. | Jamila Josip Borda, Kirsten Matheus, Friedel Gerfers |
| 2022 | ETFA | Characterization of Multi-Gigabit Automotive Ethernet Channel Radiated Emissions in Relation to ECU PCB Shield-Ground Implementations. | Jamila Josip Borda, Kirsten Matheus, Friedel Gerfers |
| 2022 | ISCAS | PAM-4/6/8 Performance and Power Analysis for Next Generation 224Gbit/s Links. | Urs Hecht, Enne Wittenhagen, Halil Cirit, Saman Behtash, Srinivas Venkataram, Friedel Gerfers |
| 2022 | ISCAS | In-Vehicle Network Standards - Overview and Implementation Examples. | Helia Ordouei, Friedel Gerfers, Silvio Waldmann |
| 2022 | ISCAS | A novel OFDM-based Radar and Communication System Design using Digital IQ-Modulation and 52 GS/s Direct-RF Data Converter. | Silvio Waldmann, Helia Ordouei, Friedel Gerfers |
| 2021 | ISCAS | A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS. | Frowin Buballa, Sebastian Linnhoff, Michael Reinhold, Friedel Gerfers |
| 2021 | ISCAS | A 56 GHz 19 fs RMS-Jitter Sub-Sampling Phase-Locked Loop for 112 Gbit/s Transceivers. | Patrick Kurth, Kai Misselwitz, Urs Hecht, Friedel Gerfers |
| 2021 | ISCAS | A 12 Bit 8 GS/s Randomly-Time-Interleaved SAR ADC with Adaptive Mismatch Correction. | Sebastian Linnhoff, Erik Sippel, Frowin Buballa, Michael Reinhold, Martin Vossiek, Friedel Gerfers |
| 2020 | ISCAS | Towards pW-Class IoT Nodes using Crystalline Oxide Semiconductor Dynamic Logic. | Tobias Kaiser, Friedel Gerfers |
| 2020 | ISCAS | A DAC Linearization Technique Enabling 15-Bit INL through Adaptive Body-Biasing in 22FDX. | Marcel Runge, Dario Schmock, Enne Wittenhagen, Friedel Gerfers |
| 2020 | ISCAS | A Power Efficient Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks. | Suhas Shivapakash, Hardik Jain, Olaf Hellwich, Friedel Gerfers |
| 2020 | ISCAS | A Sub-Sampling Beam-Forming Summation Track and Hold for Software Defined Radio. | Enne Wittenhagen, Marcel Runge, Wilhelm Keusgen, Friedel Gerfers |
| 2019 | FIE | High Performance Electronic Design Education - from Technology towards High Frequency Chip Sets. | Andreas Mai, Philipp Scholz, Gerhard G. Fischer, Friedel Gerfers |
| 2019 | ISCAS | A Single-Channel 18.5 GS/s 5-bit Flash ADC using a Body-Biased Comparator Architecture in 22nm FD-SOI. | Nima Lotfi, Pedro Lehmann Ibez, Marcel Runge, Friedel Gerfers |
| 2019 | ISCAS | Optimized Zero Placement within Noise Coupling Transfer Functions for Oversampled ADCs. | Marcel Runge, Nima Lotfi, Friedel Gerfers |
| 2018 | ISCAS | Correlation Based Time-Variant DAC Error Estimation in Continuous-Time ∑Δ ADCs With Pseudo Random Noise. | Marcel Runge, Friedel Gerfers |
| 2017 | ISCAS | A digital calibration technique canceling non-linear switch and package impedance effects of a 1.6GS/s TX-DAC in 28 nm CMOS. | Hossein Ghafarian, Friedel Gerfers |
| 2017 | ISCAS | A digital compensation method canceling static and non-linear time-variant feedback DAC errors in ΣΔ analog-to-digital converters. | Marcel Runge, Friedel Gerfers |
| 2016 | ISCAS | Implementation and design investigation of 40 Gbps driver IC for silicon photonics ring-modulator in SiGe 130-nm. | Adel Fatemi, Heinrich Klar, Friedel Gerfers |
| 2006 | ISCAS | A transistor-based clock jitter insensitive DAC architecture. | Friedel Gerfers, Maurits Ortmanns, P. Schmitz |
| 2006 | ISCAS | An infinite-skew tolerant delay locked loop. | Pavel V. Petkov, Jim E. Conder, Friedel Gerfers |
| 2005 | ISCAS | A new technique for automatic error correction in Sigma-Delta modulators. | Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli |
| 2005 | ISCAS | Increased jitter sensitivity in continuous- and discrete-time Sigma-Delta modulators due to finite opamp settling speed. | Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli |
| 2004 | ISCAS | Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators. | Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli |
| 2004 | ISCAS | A calibration method for current steering digital to analog converters in continuous time multi-bit sigma delta modulators. | Matthias Keller, Yiannos Manoli, Friedel Gerfers |
| 2004 | ISCAS | A cascaded continuous-time Sigma Delta modulator with 80 dB dynamic range. | Maurits Ortmanns, Markus Kuderer, Yiannos Manoli, Friedel Gerfers |
| 2003 | ISCAS | A 1 V, 12-bit wideband continuous-time ΣΔ modulator for UMTS applications. | Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli |
| 2003 | ISCAS | Influence of finite integrator gain bandwidth on continuous-time sigma delta modulators. | Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli |
| 2003 | ISCAS | Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators. | Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli |
| 2002 | ISCAS | Figure of merit based design strategy for low-power continuous-time Sigma-Delta modulators. | Friedel Gerfers, Kian Min Soh, Maurits Ortmanns, Yiannos Manoli |
| 2002 | ISCAS | Multirate cascaded continuous time Sigma-Delta modulators. | Maurits Ortmanns, Lourans Samid, Yiannos Manoli, Friedel Gerfers |
| 2002 | ISCAS | A new kind of low-power multibit third order continuous-time lowpass Sigma-Delta modulator. | Lourans Samid, Maurits Ortmanns, Yiannos Manoli, Friedel Gerfers |
| 2001 | DATE | A design strategy for low-voltage low-power continuous-time sigma-delta A/D converters. | Friedel Gerfers, Yiannos Manoli |
| 2001 | ISCAS | On the synthesis of cascaded continuous-time Sigma-Delta modulators. | Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli |
| 2000 | ISLPED | A 1.5V low-power third order continuous-time lowpass Sigma-Delta A/D converter (poster session). | Friedel Gerfers, Yiannos Manoli |