| 2021 | ARITH | FPGA acceleration of bit-true simulations for word-length optimization. | Javier Hormigo, Gabriel Caffarena |
| 2019 | FPL | High-Performance Decoding of Variable-Length Memory Data Packets for FPGA Stream Processing. | Roberto Sierra, Filippo Mangani, Carlos Carreras, Gabriel Caffarena |
| 2006 | FPL | High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs. | Gabriel Caffarena, Juan A. Lpez, Carlos Carreras, Octavio Nieto-Taladriz |
| 2006 | FPL | Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver. | Angel Fernandez Herrero, Alberto Jimenez-Pacheco, Gabriel Caffarena, Javier Casajs-Quirs |
| 2004 | FCCM | A Generator of High-Speed Floating-Point Modules. | Gerardo Leyva, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz |
| 2004 | FPGA | High-speed systolic array for gene matching. | Gabriel Caffarena, Slobodan Bojanic, Juan A. Lpez, Carlos E. Pedreira, Octavio Nieto-Taladriz |
| 2003 | ISCAS | Fast characterization of the noise bounds derived from coefficient and signal quantization. | Juan A. Lpez, Carlos Carreras, Gabriel Caffarena, Octavio Nieto-Taladriz |