Ganapathy Parthasarathy
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
15
Venues
10
Active years
1998–2026
Best venue rank
A*
Where they publish
Papers
15 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | IOLTS | Evaluating Generative AI for Functional Safety Analysis of Integrated Circuits. | Mouadh Ayache, Alessandra Nardi, Aditya Raj Singh, Brian Davenport, Ganapathy Parthasarathy, Teo Cupaiuolo, Mladen Berekovic, Saleh Mulhem |
| 2022 | ASPDAC | RTL Regression Test Selection using Machine Learning. | Ganapathy Parthasarathy, Aabid Rushdi, Parivesh Choudhary, Saurav Nanda, Malan Evans, Hansika Gunasekara, Sridhar Rajakumar |
| 2022 | ICCD | Optimizing ML Classification Models for Constrained EDA Resource Budgets. | Ganapathy Parthasarathy, Bhuvnesh Kumar, Saurav Nanda, Parivesh Choudhary, Sridhar Rajakumar |
| 2019 | EuroPar | Resource Aware Scheduling for EDA Regression Jobs. | Saurav Nanda, Ganapathy Parthasarathy, Parivesh Choudhary, Arun Venkatachar |
| 2005 | DAC | Structural search for RTL with predicate learning. | Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer |
| 2005 | DATE | Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver. | Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng |
| 2005 | DATE | An Efficient Sequential SAT Solver With Improved Search Strategies. | Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen |
| 2005 | ICCAD | RTL SAT simplification by Boolean and interval arithmetic reasoning. | Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer |
| 2004 | ASPDAC | Efficient reachability checking using sequential SAT. | Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang |
| 2004 | DAC | An efficient finite-domain constraint solver for circuits. | Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang |
| 2003 | ICCAD | SATORI - A Fast Sequential SAT Engine for Circuits. | Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng |
| 2002 | ITC | Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. | Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir |
| 2001 | ICCAD | Interconnect Resource-Aware Placement for Hierarchical FPGAs. | Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska |
| 1999 | VLSID | Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. | Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss |
| 1998 | VTS | Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. | Ganapathy Parthasarathy, Michael L. Bushnell |