Geert Van der Plas
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
16
Venues
7
Active years
1997–2023
Best venue rank
A*
Where they publish
Papers
16 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2023 | DATE | NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips. | Xabier Iturbe, Nassim Abderrahmane, Jaume Abella, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Anglica Dvila, Arne Erdmann, Carles Estrada, Ander Fernndez, Anna Fontanelli, Jos Flich, Gianluca Furano, Alejandro Hernn Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernndez, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernab Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Lujn, Karel Masark, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov |
| 2013 | ASPDAC | Design issues in heterogeneous 3D/2.5D integration. | Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne |
| 2011 | DAC | 3D heterogeneous system integration: application driver for 3D technology development. | Eric Beyne, Pol Marchal, Geert Van der Plas |
| 2011 | DATE | An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations. | Geert Eneman, J. Cho, V. Moroz, Dragomir Milojevic, M. Choi, Kristin De Meyer, Abdelkarim Mercha, Eric Beyne, Thomas Hoffmann, Geert Van der Plas |
| 2010 | IOLTS | 3D integration: Circuit design, test, and reliability challenges. | Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal |
| 2008 | DATE | Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications. | Pierluigi Nuzzo, Claudio Nani, Sergio Saponara, Luca Fanucci, Geert Van der Plas |
| 2007 | DATE | Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's. | Stephane Bronckers, Charlotte Soens, Geert Van der Plas, Gerd Vandersteen, Yves Rolain |
| 2007 | ISCAS | Scalable Gate-Level Models for Power and Timing Analysis. | Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stphane Donnay, Georges G. E. Gielen, Hugo De Man |
| 2006 | DAC | A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW. | Pierluigi Nuzzo, Geert Van der Plas, Fernando De Bernardinis, Liesbet Van der Perre, Bert Gyselinckx, Pierangelo Terreni |
| 2005 | DATE | Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. | Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stphane Donnay |
| 2004 | DAC | High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. | Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovoln, Piet Wambacq, Stphane Donnay, Georges G. E. Gielen, Hugo De Man |
| 2004 | DATE | Digital Ground Bounce Reduction by Phase Modulation of the Clock. | Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stphane Donnay, Georges G. E. Gielen, Hugo De Man |
| 2001 | ICCAD | A Layout-Aware Synthesis Methodology for RF Circuits. | Peter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen |
| 2000 | DAC | Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter. | Geert Van der Plas, Jan Vandenbussche, Walter Daems, Antal van den Bosch, Georges G. E. Gielen, Willy M. C. Sansen |
| 2000 | DAC | CYCLONE: automated design and layout of RF LC-oscillators. | Carl De Ranter, Bram De Muer, Geert Van der Plas, Peter J. Vancorenland, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen |
| 1997 | VTS | Automated test pattern generation for analog integrated circuits. | Wim Verhaegen, Geert Van der Plas, Georges G. E. Gielen |