Gourav Modi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2016–2017
Best venue rank
A
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | FPGA | 120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board. | Chethan Kumar H. B, Prashant Ravi, Gourav Modi, Nachiket Kapre |
| 2016 | FPL | Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletons. | Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket Kapre |