| 2026 | EuroPar | Accelerating Multi-agent Reinforcement Learning on Heterogeneous Platforms. | Samuel Wiggins, Grace Zgheib, Mahesh A. Iyer, Viktor Prasanna |
| 2026 | HPDC | FAME: A Framework for Accelerating Independent Multi-Agent Reinforcement Learning on Heterogeneous Platforms. | Samuel Wiggins, Nikunj Gupta, Grace Zgheib, Mahesh A. Iyer, Viktor K. Prasanna |
| 2025 | EuroPar | Accelerating Independent Multi-Agent Reinforcement Learning on Multi-GPU Platforms. | Samuel Wiggins, Nikunj Gupta, Grace Zgheib, Mahesh A. Iyer, Viktor K. Prasanna |
| 2025 | FCCM | A Partitioning-Based CAD Flow for Interposer-Based Multi-Die FPGAs. | Mahesh A. Iyer, Andrew B. Kahng, Jason Luu, Bodhisatta Pramanik, Kristofer Vorwerk, Grace Zgheib |
| 2025 | FPL | Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. | Junius Pun, Xilai Dai, Grace Zgheib, Mahesh A. Iyer, Andrew Boutros, Vaughn Betz, Mohamed S. Abdelfattah |
| 2025 | ICPADS | ARC: A Runtime Engine for Accelerating Independent Multi-Agent Reinforcement Learning on Multi-Core Processors. | Samuel Wiggins, Nikunj Gupta, Grace Zgheib, Mahesh A. Iyer, Viktor K. Prasanna |
| 2021 | FPL | Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming. | Grace Zgheib, Yu Shen Lu, Ilya Ganusov |
| 2020 | FPGA | Architectural Enhancements in Intel Agilex™ FPGAs. | Jeffrey Chromczak, Mark Wheeler, Charles Chiasson, Dana How, Martin Langhammer, Tim Vanderhoek, Grace Zgheib, Ilya Ganusov |
| 2020 | FPGA | Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing. | Stefan Nikolic, Grace Zgheib, Paolo Ienne |
| 2020 | FPL | Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. | Stefan Nikolic, Grace Zgheib, Paolo Ienne |
| 2019 | FPL | Finding a Needle in the Haystack of Hardened Interconnect Patterns. | Stefan Nikolic, Grace Zgheib, Paolo Ienne |
| 2017 | FPGA | NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. | Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang |
| 2017 | FPL | Evaluating FPGA clusters under wide ranges of design parameters. | Grace Zgheib, Paolo Ienne |
| 2016 | FPGA | FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures. | Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne |
| 2015 | FPL | A technology mapper for depth-constrained FPGA logic cells. | Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne |
| 2015 | IRI | An Ant Colony Optimization Heuristic to Optimize Prediction of Stability of Object-Oriented Components. | Haidar M. Harmanani, Danielle Azar, Grace Zgheib, David Kozhaya |
| 2014 | FPGA | Revisiting and-inverter cones. | Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne |
| 2013 | FPGA | Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). | Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne |
| 2013 | FPL | Shadow And-Inverter Cones. | Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne |
| 2011 | FPGA | Reducing the pressure on routing resources of FPGAs with generic logic chains. | Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne |