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H. Udayakumar

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

9

Venues

3

Active years

1999–2009

Best venue rank

National

Where they publish

Papers

9 indexed papers, newest first.

YearVenueTitleAuthors
2009VLSIDAn Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis.Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind
2008ISLPEDClock gating for power optimization in ASIC design cycle theory & practice.Sukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao
2006VLSIDA Methodology for Switching Activity Based IO Powerpad Optimisation.Snehashis Roy, Sukumar Jairam, H. Udayakumar
2005VLSIDA Methodology for Fast Vector Based Power Supply and Substrate Noise Analyses.Sankar P. Debnath, Sukumar Jairam, H. Udayakumar
2004VLSIDPackage-silicon co-design - Experiment with an SOC design.P. R. Suresh, P. K. Sundararajan, Anshuli Goel, H. Udayakumar, C. Srinivasan, Vasudev Sinari, Raghavendrakumar Ravinutala
2002VLSIDChallenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon.Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji
2000VLSIDA Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores.Karthikeyan Madathil, Jagdish C. Rao, Subash Chandar G., Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar
1999ICCDA Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology.Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash Chandar G.
1999VLSIDA Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors.Avinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar