Harald P. E. Vranken
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
20
Venues
10
Active years
1994–2018
Best venue rank
A*
Where they publish
Papers
20 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | SAC | Applying deep learning on packet flows for botnet detection. | Jos van Roosmalen, Harald P. E. Vranken, Marko C. J. D. van Eekelen |
| 2016 | SECRYPT | User-friendly Manual Transfer of Authenticated Online Banking Transaction Data - A Case Study that Applies the What You Enter Is What You Sign Transaction Authorization Information Scheme. | Sven Kiljan, Harald P. E. Vranken, Marko C. J. D. van Eekelen |
| 2014 | CSEDU | An Exercise Assistant for Practical Networking and IT Security Courses in Higher Education. | Jens Haag, Stefan Karsch, Harald P. E. Vranken, Marko C. J. D. van Eekelen |
| 2014 | CSEDU | An Exercise Assistant for Practical Networking Courses. | Jens Haag, Christian Witte, Stefan Karsch, Harald P. E. Vranken, Marko C. J. D. van Eekelen |
| 2011 | CLOSER | The Impact of Server Virtualization on ITIL Processes. | Jurriaan Kamer, Harald P. E. Vranken |
| 2011 | CSEDU | A Distributed Virtual Computer Security Lab. | Harald P. E. Vranken, Jens Haag, Tobias Horsmann, Stefan Karsch |
| 2008 | ITiCSE | Experiences with a synchronous virtual classroom in distance education. | Herman Koppelman, Harald P. E. Vranken |
| 2006 | DAC | Fault detection and diagnosis with parity trees for space compaction of test responses. | Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jrgen Schlffel, Friedrich Hapke |
| 2004 | DATE | Impact of Test Point Insertion on Silicon Area and Timing during Layout. | Harald P. E. Vranken, Ferry Syafei Sapei, Hans-Joachim Wunderlich |
| 2004 | ITC | Efficient Pattern Mapping for Deterministic Logic BIST. | Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers |
| 2004 | ITC | X-Masking During Logic BIST and Its Impact on Defect Coverage. | Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker |
| 2003 | ETS | Yield analysis for repairable embedded memories. | Anuja Sehgal, Aishwarya Dubey, Erik Jan Marinissen, Clemens Wouters, Harald P. E. Vranken, Krishnendu Chakrabarty |
| 2003 | ITC | ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume. | Harald P. E. Vranken, Friedrich Hapke, Soenke Rogge, Domenico Chindamo, Erik H. Volkerink |
| 2002 | ETS | Combining deterministic logic BIST with test point insertion. | Harald P. E. Vranken, Florian Meister, Hans-Joachim Wunderlich |
| 2001 | DATE | Circuit partitioning for efficient logic BIST synthesis. | Alexander Irion, Gundolf Kiefer, Harald P. E. Vranken, Hans-Joachim Wunderlich |
| 2001 | ITC | Enhanced reduced pin-count test for full-scan design. | Harald P. E. Vranken, Tom Waayers, Hrv Fleury, David Lelouvier |
| 2000 | ITC | Application of deterministic logic BIST on industrial circuits. | Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen |
| 1999 | ETS | Debug facilities in the TriMedia CPU64 architecture. | Harald P. E. Vranken |
| 1999 | ICCD | TriMedia CPU64 Architecture. | Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel |
| 1994 | ITC | System-Level Testability of Hardware/Software Systems. | Harald P. E. Vranken, M. P. J. Stevens, M. T. M. Segers, J. H. M. M. van Rhee |