Henri Fraisse
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
1993–2020
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2020 | FPL | A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs. | Abhishek Kumar Jain, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde |
| 2018 | FPL | A SAT-based Timing Driven Place and Route Flow for Critical Soft IP. | Henri Fraisse, Dinesh Gaitonde |
| 2016 | FPGA | Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network. | Henri Fraisse, Abhishek Joshi, Dinesh Gaitonde, Alireza Kaviani |
| 2016 | FPL | Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs. | Ilya Ganusov, Henri Fraisse, Aaron Ng, Rafael Trapani Possignolo, Sabya Das |
| 1993 | DAC | A New Viewpoint on Two-Level Logic Minimization. | Olivier Coudert, Jean Christophe Madre, Henri Fraisse |