Hiroki Matsutani
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
55
Venues
23
Active years
2005–2026
Best venue rank
A*
Where they publish
- CPDP9 papers
- BFPL6 papers
- BEuroPar5 papers
- BASPDAC4 papers
- CISPA4 papers
- A*HPCA4 papers
- BICPP3 papers
- BRTCSA3 papers
- BICPADS2 papers
- NationalPDPTA2 papers
- CBSN1 paper
- CHPCC1 paper
- A*DAC1 paper
- BNCA1 paper
- NationalVTS1 paper
- CCLUSTER1 paper
- NationalHOTI1 paper
- NationalVLSID1 paper
- BTrustCom1 paper
- ADATE1 paper
- CICA3PP1 paper
- A*ISCA1 paper
- A*MICRO1 paper
Papers
55 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | EuroPar | Layer-Wise CPU-GPU Scheduling for LLM Inference on Memory-Limited Consumer GPUs. | Naoto Sugiura, Yuta Tokusashi, Hiroki Matsutani |
| 2025 | ASPDAC | Skip2-LoRA: A Lightweight On-device DNN Fine-tuning Method for Low-cost Edge Devices. | Hiroki Matsutani, Masaaki Kondo, Kazuki Sunaga, Radu Marculescu |
| 2024 | BSN | A Tiny Supervised ODL Core with Auto Data Pruning for Human Activity Recognition. | Hiroki Matsutani, Radu Marculescu |
| 2023 | PDP | An Efficient Accelerator for Deep Learning-based Point Cloud Registration on FPGAs. | Keisuke Sugiura, Hiroki Matsutani |
| 2022 | HPCC | ONLAD-IDS: ONLAD-Based Intrusion Detection System Using SmartNIC. | Man Wu, Hiroki Matsutani, Masaaki Kondo |
| 2022 | PDP | Accelerating Distributed Deep Reinforcement Learning by In-Network Experience Sampling. | Masaki Furukawa, Hiroki Matsutani |
| 2022 | PDP | dsODENet: Neural ODE and Depthwise Separable Convolution for Domain Adaptation on FPGAs. | Hiroki Kawakami, Hirohisa Watanabe, Keisuke Sugiura, Hiroki Matsutani |
| 2021 | PDP | Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. | Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi |
| 2020 | EuroPar | An Edge Attribute-Wise Partitioning and Distributed Processing of R-GCN Using GPUs. | Tokio Kibata, Mineto Tsukada, Hiroki Matsutani |
| 2020 | PDP | Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch. | Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani |
| 2019 | DAC | Sparse 3-D NoCs with Inductive Coupling. | Michihiro Koibuchi, Lambert T. Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova |
| 2018 | EuroPar | Accelerating Online Change-Point Detection Algorithm Using 10 GbE FPGA NIC. | Takuma Iwata, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani |
| 2018 | EuroPar | OS-ELM-FPGA: An FPGA-Based Online Sequential Unsupervised Anomaly Detector. | Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani |
| 2018 | ISPA | Acceleration of Anomaly Detection in Blockchain Using In-GPU Cache. | Shin Morishima, Hiroki Matsutani |
| 2018 | ISPA | Network Optimizations on Prediction Server with Multiple Predictors. | Kaho Okuyama, Yuta Tokusashi, Takuma Iwata, Mineto Tsukada, Kazumasa Kishiki, Hiroki Matsutani |
| 2018 | ISPA | Accelerating Blockchain Transfer System Using FPGA-Based NIC. | Yuma Sakakibara, Yuta Tokusashi, Shin Morishima, Hiroki Matsutani |
| 2018 | NCA | Low-Reliable Low-Latency Networks Optimized for HPC Parallel Applications. | Truong Thao Nguyen, Hiroki Matsutani, Michihiro Koibuchi |
| 2018 | PDP | Accelerating Blockchain Search of Full Nodes Using GPUs. | Shin Morishima, Hiroki Matsutani |
| 2018 | VTS | Special session on bringing cores closer together: The wireless revolution in on-chip communication. | Terrence S. T. Mak, Hiroki Matsutani, Partha Pratim Pande |
| 2017 | CLUSTER | A Case for Uni-directional Network Topologies in Large-Scale Clusters. | Michihiro Koibuchi, Tomohiro Totoki, Hiroki Matsutani, Hideharu Amano, Fabien Chaix, Ikki Fujiwara, Henri Casanova |
| 2017 | FPL | In-switch approximate processing: Delayed tasks management for MapReduce applications. | Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani |
| 2017 | HPCA | High-Bandwidth Low-Latency Approximate Interconnection Networks. | Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi |
| 2017 | ICPADS | HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. | Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
| 2017 | ICPP | Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. | Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano |
| 2017 | PDP | An FPGA-based In-NIC Cache Approach for Lazy Learning Outlier Filtering. | Ami Hayashi, Hiroki Matsutani |
| 2016 | EuroPar | Distributed In-GPU Data Cache for Document-Oriented Data Store via PCIe over 10 Gbit Ethernet. | Shin Morishima, Hiroki Matsutani |
| 2016 | HOTI | A Multilevel NOSQL Cache Design Combining In-NIC and In-Kernel Caches. | Yuta Tokusashi, Hiroki Matsutani |
| 2016 | ICPADS | Accelerating Spark RDD Operations with Local and Remote GPU Devices. | Yasuhiro Ohno, Shin Morishima, Hiroki Matsutani |
| 2016 | ICPP | Randomly Optimized Grid Graph for Low-Latency Interconnection Networks. | Koji Nakano, Daisuke Takafuji, Satoshi Fujita, Hiroki Matsutani, Ikki Fujiwara, Michihiro Koibuchi |
| 2016 | PDP | Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. | Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
| 2016 | VLSID | The Future of NoCs: New Technologies and Architectures. | Partha Pratim Pande, Sudeep Pasricha, Hiroki Matsutani |
| 2015 | HPCA | Augmenting low-latency HPC network with free-space optical links. | Ikki Fujiwara, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanova |
| 2015 | PDP | Optimized Core-Links for Low-Latency NoCs. | Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi |
| 2015 | TrustCom | Performance Evaluations of Document-Oriented Databases Using GPU and Cache Structure. | Shin Morishima, Hiroki Matsutani |
| 2014 | DATE | Low-latency wireless 3D NoCs via randomized shortcut chips. | Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano |
| 2013 | ASPDAC | A case for wireless 3D NoCs for CMPs. | Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano |
| 2013 | FPL | Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. | Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura |
| 2013 | HPCA | Layout-conscious random topologies for HPC off-chip interconnects. | Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova |
| 2013 | ICA3PP | A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by Maximizing Topological Regularity. | Daisuke Sasaki, Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
| 2012 | ASPDAC | A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. | Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano |
| 2012 | FPL | CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. | Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura |
| 2012 | ISCA | A case for random shortcut topologies for HPC interconnects. | Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova |
| 2011 | RTCSA | Dynamic Voltage and Frequency Scaling for Real-Time Scheduling on a Prioritized SMT Processor. | Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki |
| 2011 | RTCSA | Design and Implementation of On-Chip Adaptive Router with Predictor for Regional Congestion. | Masakazu Taniguchi, Hiroki Matsutani, Nobuyuki Yamasaki |
| 2011 | RTCSA | A Dynamic Link-Width Optimization for Network-on-Chip. | Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano |
| 2010 | MICRO | A variable-pipeline on-chip router optimized to traffic pattern. | Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
| 2009 | FPL | MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. | Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano |
| 2009 | HPCA | Prediction router: Yet another low latency on-chip router architecture. | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga |
| 2009 | PDPTA | An On/Off Link Activation Method for Power Regulation in InfiniBand. | Jos Miguel Montaana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano |
| 2008 | ASPDAC | Run-time power gating of on-chip routers using look-ahead routing. | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang |
| 2008 | FPL | A link removal methodology for Networks-on-Chip on reconfigurable systems. | Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi |
| 2007 | FPL | A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. | Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
| 2007 | ICPP | Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
| 2006 | ISPA | Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
| 2005 | PDPTA | Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |