| 2020 | FCCM | Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs. | Akira Jinguji, Shimpei Sato, Hiroki Nakahara |
| 2020 | FCCM | High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression. | Hiroki Nakahara, Zhiqiang Que, Wayne Luk |
| 2020 | FCCM | Optimizing Reconfigurable Recurrent Neural Networks. | Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk |
| 2020 | FPGA | R2CNN: Recurrent Residual Convolutional Neural Network on FPGA. | Hiroki Nakahara, Zhiqiang Que, Akira Jinguji, Wayne Luk |
| 2020 | FPL | An FPGA-Based Low-Latency Accelerator for Randomly Wired Neural Networks. | Ryosuke Kuramochi, Hiroki Nakahara |
| 2019 | FPGA | An FPGA-based Fine Tuning Accelerator for a Sparse CNN. | Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato |
| 2019 | FPL | Real-Time Multi-Pedestrian Detection in Surveillance Camera using FPGA. | Akira Jinguji, Youki Sada, Hiroki Nakahara |
| 2019 | FPL | FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. | Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato |
| 2019 | FPL | An FPGA Implementation of Real-Time Object Detection with a Thermal Camera. | Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Hiroki Nakahara |
| 2018 | FPGA | A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA. | Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato |
| 2018 | FPL | A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2). | Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato |
| 2018 | FPL | Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs. | Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara |
| 2018 | ISCAS | A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector. | Hiroki Nakahara, Tsutomu Sasao |
| 2017 | FPGA | A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). | Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura |
| 2017 | FPL | A fully connected layer elimination for a binarizec convolutional neural network on an FPGA. | Hiroki Nakahara, Tomoya Fujii, Shimpei Sato |
| 2015 | FPL | A deep convolutional neural network based on nested residue number system. | Hiroki Nakahara, Tsutomu Sasao |
| 2013 | FPL | A packet classifier using LUT cascades based on EVMDDS (k). | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura |
| 2012 | ICA3PP | On a Wideband Fast Fourier Transform Using Piecewise Linear Approximations: Application to a Radio Telescope Spectrometer. | Hiroki Nakahara, Hiroyuki Nakanishi, Tsutomu Sasao |
| 2010 | DSD | A Packet Classifier Using a Parallel Branching Program Machine. | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura |
| 2009 | DSD | The Parallel Sieve Method for a Virus Scanning Engine. | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura |
| 2009 | FPL | A virus scanning engine using a parallel finite-input memory machine and MPUs. | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura |
| 2006 | ASPDAC | A fast logic simulator using a look up table cascade emulator. | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura |